.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 250 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 +- 2 files changed, 251 insertions(+), 1 deletion(-)
Add nodes for the two additional TC9563 PCIe switches present on the
QCOM RB3Gen2 Industrial Mezzanine platform.
One of the TC9563 is connected directly to the PCIe0 root-port while
the second TC9563 switch is connected in cascade fashion to another
already available TC9563 switch on PCIe1 via the former's downstream
port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
would look something like below:
┌────────────────────────────┐
│ │
│ │
│ │
│ SoC │
│ │
│ PCIe0 PCIe1 │
│ ┌───┐ ┌───┐ │
└────└─┬─┘───────────└─┬─┘───┘
│ │
│ │
│ │
┌────────────────┘ └────────────────┐
│ │
│ │
│ │
┌────────┴─────────┐ ┌──────────┴───────┐
│ USP │ │ USP │
│ │ │ │
│ TC9563 │ │ TC9563 │
│ │ │ │
│ │ │ │
│ DSP1 DSP2 DSP3 │ │ DSP1 DSP2 DSP3 │
└──┬──────┬─────┬──┘ └───┬─────┬─────┬──┘
│ │ │ │ │ │
│ │ │ │ │ │
│ │ │ │ │ │
│ │ │ │ EP ETHERNET
│ │ │ │
│ │ │ └──────┐
EP EP ETHERNET │
│
│
┌─────────┴────────┐
│ USP │
│ │
│ TC9563 │
│ │
│ │
│ DSP1 DSP2 DSP3 │
└──┬──────┬─────┬──┘
│ │ │
│ │ │
│ │ │
│ │ │
│ │ │
EP EP ETHERNET
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
Changes in v3:
- Fixed DT binding errors.
- Removed labels from unused TC9563 switch ports. (Konrad)
- Sort nodes in alphabetical order. (Dmitry)
- Fixed styling issues (Konrad)
- Link to v2: https://lore.kernel.org/r/20260203-industrial-mezzanine-pcie-v2-0-8579ed6bf931@oss.qualcomm.com
Changes in v2:
- Posted as v2 by error. Please consider as v1.
---
Sushrut Shree Trivedi (2):
arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 250 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 +-
2 files changed, 251 insertions(+), 1 deletion(-)
---
base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2
change-id: 20260131-industrial-mezzanine-pcie-75dd851f5b04
Best regards,
--
Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote: > Add nodes for the two additional TC9563 PCIe switches present on the > QCOM RB3Gen2 Industrial Mezzanine platform. > > One of the TC9563 is connected directly to the PCIe0 root-port while > the second TC9563 switch is connected in cascade fashion to another > already available TC9563 switch on PCIe1 via the former's downstream > port (DSP). The final PCIe hierarchy on the Industrial Mezz platform ^ +Mani is that PCIe terminology, or is that a Toshiba-ism? Konrad
On 2/12/2026 5:18 PM, Konrad Dybcio wrote: > On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote: >> Add nodes for the two additional TC9563 PCIe switches present on the >> QCOM RB3Gen2 Industrial Mezzanine platform. >> >> One of the TC9563 is connected directly to the PCIe0 root-port while >> the second TC9563 switch is connected in cascade fashion to another >> already available TC9563 switch on PCIe1 via the former's downstream >> port (DSP). The final PCIe hierarchy on the Industrial Mezz platform > ^ +Mani is that PCIe terminology, or is that a Toshiba-ism? The PCIe Spec actually uses the DSP terminology under r6.2 sec 7.9.29: Streamlined Virtual Channel Extended Capability (SVC) "If the SVC Extended Capability structure is implemented in a USP containing one or more Switch USP Functions, it must be implemented in all associated Switch DSP Functions" Sushrut > > Konrad
© 2016 - 2026 Red Hat, Inc.