From nobody Thu Apr 2 18:51:23 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D32C02264CA for ; Thu, 12 Feb 2026 10:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893070; cv=none; b=JCj5LY90QpAcLR8qdV3dE8Dt35MpFmtBqIJLGia7egYN7sYJMg36BJc5cXDMukN0iqXHTf7wwzwFepCB8hT+7VvVW24Y315FdPh1zy2hIuMbX77xKTPX+Yo+ZyQJvy1Qy2yQ3ipE7dRWSLQBwsjsGWUCEVdBFCMp2/CxX5wZ7q0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893070; c=relaxed/simple; bh=VfnryVwy76qfl6rcKdpgx+vFKR/El0L107AaXJ3jJVo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mf4THeDqqp3jb0fKPO9oAbJRAisPIlsUwhvge8tkpFCq35WPXCBn5jpO/F3+pBx2CLBz5k5x0m211ayY0Bg36Y0JtbNI+zWFcf02rfj78Mx/oaTDTpm4OfI++1pAjLqV2ykCzALOqQ60OyfHQBZ191wVPApFh3S9ILpBQyHt3eI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=QmK4mQos; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Jp1lBfAY; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="QmK4mQos"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Jp1lBfAY" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61CAGHXg4112098 for ; Thu, 12 Feb 2026 10:44:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ncYzEF5LnROxHmgpRG4yPJsO7MF5gr8kBl4VVLXh3pg=; b=QmK4mQosJZ/dzd5e 3Cy1QiYq3i/3Mi7bToW3/BDtbqlmNE++gGCpGDhJiKZANPrt6zJSbChZhD4PbcP0 3Z0t2Q4GU/srJhDUsFjSloS93ZTpN+tN8ayW7/r/P3KsULX+gbFbb4QSd7GMO9pN 6wAm/+xIGIN+f3fbxer3fD8IZJ5u+m4Y77fe2Tk06X2lxj7BKBVBcm7Zqk6+S5XJ k3CPd9/dljI8uvbEXJ5gP/6d+aX8Wp0gwGiNK0qzPIpfhDqEg93ie36JJL/9LZjh n1mn90bSHMCzLO9dbjnn+Y0EH29Odc9q39a8e5zRmFJ09dtCcjFuWix1ZFX/r+C4 cI9AoA== Received: from mail-pj1-f70.google.com (mail-pj1-f70.google.com [209.85.216.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c9cya8306-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 12 Feb 2026 10:44:27 +0000 (GMT) Received: by mail-pj1-f70.google.com with SMTP id 98e67ed59e1d1-35464d7c539so6345008a91.0 for ; Thu, 12 Feb 2026 02:44:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1770893067; x=1771497867; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ncYzEF5LnROxHmgpRG4yPJsO7MF5gr8kBl4VVLXh3pg=; b=Jp1lBfAYFJXcR1fAeTZ/UbSpk17tofK1Jmkkadj4I1HeawzzY6GKo/xZZOA1pYoToF GW/wI1/fkj9kv6g+pGYBHr+SEJc9vbBP4GgjfScPPNKwX4C/QOKOBjTwaRUEm78bcdz8 rwPVz4GK3UMcqhm+FRvGzqX47Qvdmpbsj5KFQF3KVu7KFWJXHKfxo40SdST0S7uyxUDU 6Ypr22mlfyQjF0p39Qbdn1XuTbrfrUsowfbS8r9yBHJEY0ugTVL7z1RF57SJLf2LN+2g UPGa4XJ+hA3BKRKFnpYheuL+7rIZwORwhMZYYyIs9er2jWaipUZjMMzbFMcNmyLMw3RV nY6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770893067; x=1771497867; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ncYzEF5LnROxHmgpRG4yPJsO7MF5gr8kBl4VVLXh3pg=; b=XsZ7thWCjIsW4mRG+wz+HtwHqZlBK6FHZ2IrEV+z0qf6BAnm1u744CWJcVy8BzQPxm dUnFVJvday9ej8p/wayuyAbPjsYTCykXrbnbix1XhRcCgynhf0ecmB/Caw6fMYJtwEpU 1BSDX89xXYKCbqU77DSWpByq9vSvfTyFDJiC1CTFApTCWjZ2V/54J+vtzWWEaVOIkbQv ZV35sR4ivvLsHVM55ivF/XOSszq6tBBc0MhENLmnkOZFhmrSM3PnZ7V3Ju2PY+sa9qHs YDbrY9ATtXSSZ4hmlh1Lw4WDiswjM9D3K7ceP1p4cyNz5WeIvR8cPE5wc3jxCmYKamfV Tzig== X-Forwarded-Encrypted: i=1; AJvYcCXAJX/HYXGDBpXYKdIXEqcEkRdD2iU2Nfy/OGsxCno3xXN3xMqwOzCzVdaFd6TgdVhyT1zhjWhPEhApJdA=@vger.kernel.org X-Gm-Message-State: AOJu0YyhHLdun8BGdoFw+Fft9T9yeVg0uIQbBzU/E8cGAAsAvicgbGtC sCayMVtgCYI6C6f68tI67ktCH15DIMYq3eZOEqkWU29GkexXnl3YMNfnt0xqaBNL3fJ24GjjAPh DCSwkCwmMAoJzl0qcK+o4nOVSJLRU7bhhUeugKbOKVbIs96z09Wrq90nWrH+Z5DlEiSobgwdpZr I= X-Gm-Gg: AZuq6aKtH7AZejlXg9y4WKAl9G+EUNechoCNq0OqQsN1WaBz9FwhxpNobmjiNChs6Cy tejqmrWmNi0tkmtt0tmWCZh3pe1LyR0ssXrDwqS3s1GfC9C28LRbs1cJJUK7WTKGeUqO4mnEBAO R5ohc5uY0/DPaWx7Iob6TvbRrwJLURWz6FtbTh0bFCn11HVNT5BXI74V8DLhYv8MtvuS15swF3B bhCThS4pL37pXmrFb04vprm8/+GJyTSep5NhMEAXOGra26yhT/6AUEz1kB5nUI5juR494sCVCTQ RZ+gHYbL+B/NZ+sqTYL6dsnTk4gmuKrIsV+Ac4nvcsIDSOCR/gEz03Oo2ACkivnEt9vVD95hyv3 DUL2qkUkBjhRPrVu0/B4/ksQjvvn0WNxfaGeXb+E7xai8UQjr5j8KkXtmrw== X-Received: by 2002:a17:90b:39cf:b0:341:88d5:a74e with SMTP id 98e67ed59e1d1-3568f525b6bmr2142687a91.29.1770893066584; Thu, 12 Feb 2026 02:44:26 -0800 (PST) X-Received: by 2002:a17:90b:39cf:b0:341:88d5:a74e with SMTP id 98e67ed59e1d1-3568f525b6bmr2142653a91.29.1770893066074; Thu, 12 Feb 2026 02:44:26 -0800 (PST) Received: from hu-sushruts-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3567e7d9537sm4983375a91.4.2026.02.12.02.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Feb 2026 02:44:25 -0800 (PST) From: Sushrut Shree Trivedi Date: Thu, 12 Feb 2026 16:14:01 +0530 Subject: [PATCH v3 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260212-industrial-mezzanine-pcie-v3-1-1e152937a76a@oss.qualcomm.com> References: <20260212-industrial-mezzanine-pcie-v3-0-1e152937a76a@oss.qualcomm.com> In-Reply-To: <20260212-industrial-mezzanine-pcie-v3-0-1e152937a76a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Sushrut Shree Trivedi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770893058; l=4365; i=sushrut.trivedi@oss.qualcomm.com; s=20251127; h=from:subject:message-id; bh=VfnryVwy76qfl6rcKdpgx+vFKR/El0L107AaXJ3jJVo=; b=LJc+idH+m1F9gIO/g0eyhXh1dbzNXwHSwlT6gs0YW65HTOK2otD88JX6WmuZT7E3Ephtx81ms 9u97foyaF6CDLiKntD1RJt1HZIaaAeZKZHZT16Sdv/MHbY5940W3lGg X-Developer-Key: i=sushrut.trivedi@oss.qualcomm.com; a=ed25519; pk=OrUHTxBaSg1oY3CtCictJ5A4bDMNLRZS1S+QfD9pdjw= X-Proofpoint-GUID: KQfFv-LpXv1h2X_OjkaUUNVnjM_erMM9 X-Authority-Analysis: v=2.4 cv=OrBCCi/t c=1 sm=1 tr=0 ts=698daf0b cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=RBLAtJqH_bkH6XPhXP4A:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: KQfFv-LpXv1h2X_OjkaUUNVnjM_erMM9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjEyMDA4MCBTYWx0ZWRfX2LPshH8orIR1 3v+GQsGmgPnNuh9kZqBnFmehkVeMVYdHB8Gwy//OiM5fQOpBTK7aJ3+8+8b2/RDW7/qJU5Y1udw 6J4b/MopCI5U9KOycpZ/XzNQUWkFGvh1uUiGxnpPuiDiYmVz9qzIjK93dDjkka5k45IoMSmu9wN 3yx4LuUODJ4NWfhXe7hK28PKZ2kS7OEFn/tcM8FrcTod/asACG8g2Cu+SmVUGQsSVgn2R4fYjxp 3N9Vt+QfqjGswVYJsjIKKVwcuHGp9BNGw3jM0zns7I4ngV5grkV1fCJoaCFQ106u5lERUuJH24t clyhCipGFT7BHWLMYADcFOLfyiyIdyOoobSxAdDZSOQikscmT8TjRpbNhNTPbi8udOw0bFuVa3H f0nMvBuGzKWXJ2HuMKCJC4fVaa6MvsH0AYXHBHs7RQIx5bi7tfNe03mFGLnxUm/zh5UOPFo83KL 7hBe9DjoaG2IQbxiEQA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-12_03,2026-02-11_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 suspectscore=0 spamscore=0 impostorscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602120080 Add a node for the TC9563 PCIe switch connected to PCIe0. The switch has three downstream ports.Two embedded Ethernet devices are present on one of the downstream ports. All the ports present in the node represent the downstream ports and embedded endpoints. Power to the TC9563 is supplied through two LDO regulators, which are on by default and are added as fixed regulators. TC9563 can be configured through I2C. Signed-off-by: Sushrut Shree Trivedi Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 145 +++++++++++++++++= ++++ 1 file changed, 145 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.= dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 619a42b5ef48..0fb89e71bf7f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -5,9 +5,45 @@ =20 /dts-v1/; /plugin/; +#include #include #include =20 +&{/} { + + vreg_0p9: regulator-vreg-0p9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_0P9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vreg_dc_12v>; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vreg_dc_12v>; + }; + + vreg_dc_12v: regulator-vreg-dc-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_DC_12V"; + regulator-min-microvolt =3D <24000000>; + regulator-max-microvolt =3D <24000000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + &spi11 { #address-cells =3D <1>; #size-cells =3D <0>; @@ -19,3 +55,112 @@ st33htpm0: tpm@0 { spi-max-frequency =3D <20000000>; }; }; + +&pcie0 { + iommu-map =3D <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>, + <0x208 &apps_smmu 0x1c04 0x1>, + <0x210 &apps_smmu 0x1c05 0x1>, + <0x218 &apps_smmu 0x1c06 0x1>, + <0x300 &apps_smmu 0x1c07 0x1>, + <0x400 &apps_smmu 0x1c08 0x1>, + <0x500 &apps_smmu 0x1c09 0x1>, + <0x501 &apps_smmu 0x1c10 0x1>; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l10c_0p88>; + vdda-pll-supply =3D <&vreg_l6b_1p2>; + + status =3D "okay"; +}; + +&pcie0_port { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vreg_0p9>; + vdd18-supply =3D <&vreg_1p8>; + vdd09-supply =3D <&vreg_0p9>; + vddio1-supply =3D <&vreg_1p8>; + vddio2-supply =3D <&vreg_1p8>; + vddio18-supply =3D <&vreg_1p8>; + + i2c-parent =3D <&i2c1 0x77>; + + resx-gpios =3D <&tlmm 78 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie0_tc9563_resx_n>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + + }; +}; + +&tlmm { + pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { + pins =3D "gpio78"; + function =3D "gpio"; + + bias-disable; + input-disable; + output-enable; + power-source =3D <0>; + }; +}; --=20 2.25.1 From nobody Thu Apr 2 18:51:23 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6565B281358 for ; Thu, 12 Feb 2026 10:44:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893073; cv=none; b=eC04L0kv4pVOGhQ1Q3YOUyojXUK2qKZOOHG9qy7vSfgXGArKNQp5HZJwk/OEFIerbKYlyjuLAGpw30ZbMUP9m0qk1hvREm614CptHLyIkTNtd41ngo3r8QyuFG+mqOB2Y82nWOvcMn16oRSXkPSQ3o46qMiMtzQ1eVnrY0qSdDk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770893073; c=relaxed/simple; bh=3/A6GRE1/3+Eg/c3/WCPO3ArI08bR9hvTP+A00w9wo0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d3PKxudYIoEiGrm+A+1FcA9auDiulM0yE771mIukn5ikFjIcKutJBWKiekyTJIMMwFXiQVfYwQjhYcUdKfG0MnbtMjuAFxcaJ2s9N3cghkd/NIVMvHKbZr3fHb6CG2tZlUrclMjxYx0eFmu8o9OhedUcPSxa7Dep/y8QAGiuzDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Vx4mjYzp; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=MuoBGYJQ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Vx4mjYzp"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="MuoBGYJQ" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 61CAFkTG008880 for ; Thu, 12 Feb 2026 10:44:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bvYzaSe3Sw0LWFTDRt+J64ZasD/UrhxsdcUzaILBJtk=; b=Vx4mjYzp/LKGZtoX sVKTfSZHi0Z3AP239wQAqO3N9K87yGrcJGiogZp2nTiiy6pOZYp3qtsmCF8p1rdZ HrAGXfZHUIy7+A5/DtNwWtGe30zNvNJZySe1ccQVQzH4rS3C48EJobN7PYysBxWK lhN+2RxNfP2xiDlBlAbEGxPx7gHL+VdNRKwIJ2uNlTuZXwq/5SVsg/IiSqtDPkTp TcRPCd5/SabdvV7Sd99F2ZSUKHbrPL5RIrJPKemOrooIqShfiVfUE0jtFWLfe4mV FupkJKG+w+RonutYe5MDfQKT8++KcJHPJjWGxoYCXZRM41xja55DSzfyhb2XuUFk /bU2Qw== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c9cy482pm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 12 Feb 2026 10:44:31 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-35621cea097so3472702a91.1 for ; Thu, 12 Feb 2026 02:44:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1770893070; x=1771497870; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bvYzaSe3Sw0LWFTDRt+J64ZasD/UrhxsdcUzaILBJtk=; b=MuoBGYJQ1zedEwG2IG7sradAwvrlzv9HAqYE5hKrN8YYCY0r+prOrLinbWeS22R2Lo WSeAj03/xwI+C0aPEEvVGMdRhThTsnUMkFwBe3TKl34VgooZOpD8D4xzL9NkW05Ba/05 oD0MoBlohl61Co9XwC2dSkpJbwnm/Tg4kBR5C/rfEfujkT0R+CaiA8N8YnjxGtFl9IrT jRj2o9q9hJRQEXpV6kQB6F41wbhiVBlnjPEgDdysjuT29tj1JK7I/7rDCu42CxlaLdZF jZHVk35+ph9kfuMxo1QmJj2H6xvabnslYaR9bepB40KX+BFC233xXnXyRBUT8F2v170A 0vGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770893070; x=1771497870; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=bvYzaSe3Sw0LWFTDRt+J64ZasD/UrhxsdcUzaILBJtk=; b=DRfyMNkvR8tDtXWxP7dlkK68tCQ56m3NiS1G6i1ScMa5C/4lgbJahXahCc5YwvdXSu leWreENUwFGtxeC+mNDqej1eyBZ63ot1KxNVBdDmJFabv6AIF/3AIhcM13e0ck6cLp9i 5Ozcq5QQ6zhSJoT5M7LDEOeQ3/1LF8qXb3Rs/I6F3hZfwTDhpX4GQuvzlXcgCuaOSGra tuLxK4NtOtbyS9Yqg0ZOhFdaxoHkJ2wE8OrERkvTkt1PFUjvsse5m/yxhkYviVSKukgk rcBSlc0e7DLfIvv0rqVbuIDIf0Yg7jQYfEcIXKHJRnNX6Eld/lrB3QmzZ2RNsCqYGySo qfZQ== X-Forwarded-Encrypted: i=1; AJvYcCXaLtOrxnrbBlXLmNiG5okLRsjfY1qvATml1kMgY1d+C+EaG9mOxJGWRN8g5enDqBEiDHF1VJwkFmzZB3k=@vger.kernel.org X-Gm-Message-State: AOJu0YzZpC+2O5bDqLCpN8tKVnX4pRpPdgDh6LATwKcIRD93YYzGoWse S4O40XmxACmfp9F1sLsfjM5zul1S2v+6xNm3lWnIafA0ai7LrlGSKKANs1GwKZ778SFTcETzXaz eONz1i03YT9n+y96dnPROLPoR7KZIisHVPVB5lrzetSHF5FkoBzV4sZkPjkfK2uDZs61F/ANNXh 8= X-Gm-Gg: AZuq6aILV59P/bX2PrFfgOCdm3hGvfDzbLZ1pbSqt+l7V5QVgfZfshCl8YNbm90z68o PtStwBeDSGyWIXdUeV7kokCsVf9+Xh/CxkDSKou+XDjiDBnGfDiLsaKi58ZVxdZPvFsm2zes3PD Qy1742kUxeBO/l+icrrji7Dj3CJBe5Uup6fTRJyVgTnn9X5Y08FYWjs4aV1vTZV1Wk2E+YRhCGc phe8DG9GpPaJ5+hd1Bmf4bgYOuKd7cedJifO+pGvqGivylOKRlosMobROrPdGo8ux05cj2Lt4yI eAoJihQreht9f8Hu5KbrTnWvSHi7MzmkuvAFwOlHiGrDTJg+aQwCb/TxLa76Er2JtHvb0pRTg8f 7mZCzRZ4SRxZa3CWZQoSdjc7Soqwq4a/GRk+NUfIdZqFviu2pQcMGMe8SzQ== X-Received: by 2002:a17:90b:1b43:b0:356:2132:67bf with SMTP id 98e67ed59e1d1-3568f3eed82mr1938950a91.18.1770893070012; Thu, 12 Feb 2026 02:44:30 -0800 (PST) X-Received: by 2002:a17:90b:1b43:b0:356:2132:67bf with SMTP id 98e67ed59e1d1-3568f3eed82mr1938934a91.18.1770893069540; Thu, 12 Feb 2026 02:44:29 -0800 (PST) Received: from hu-sushruts-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3567e7d9537sm4983375a91.4.2026.02.12.02.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Feb 2026 02:44:29 -0800 (PST) From: Sushrut Shree Trivedi Date: Thu, 12 Feb 2026 16:14:02 +0530 Subject: [PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260212-industrial-mezzanine-pcie-v3-2-1e152937a76a@oss.qualcomm.com> References: <20260212-industrial-mezzanine-pcie-v3-0-1e152937a76a@oss.qualcomm.com> In-Reply-To: <20260212-industrial-mezzanine-pcie-v3-0-1e152937a76a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Sushrut Shree Trivedi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770893058; l=4309; i=sushrut.trivedi@oss.qualcomm.com; s=20251127; h=from:subject:message-id; bh=3/A6GRE1/3+Eg/c3/WCPO3ArI08bR9hvTP+A00w9wo0=; b=jqccJ8qaFq0Ai1Z6aqCgjlxJcyZC175CWkRkjITiBledJ/0o1b7ceafRZguklbbj63r6leet1 3UxG0jJW5ESAp88bXZpW/L0BqtW1tYGpOo0L1fT1PJVUT5GwOsXaHyN X-Developer-Key: i=sushrut.trivedi@oss.qualcomm.com; a=ed25519; pk=OrUHTxBaSg1oY3CtCictJ5A4bDMNLRZS1S+QfD9pdjw= X-Proofpoint-ORIG-GUID: M_XCjDrbaoMoZ0psDq58Y5IOX6UTBaKq X-Proofpoint-GUID: M_XCjDrbaoMoZ0psDq58Y5IOX6UTBaKq X-Authority-Analysis: v=2.4 cv=XvX3+FF9 c=1 sm=1 tr=0 ts=698daf0f cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=bvgCVipTNhjOeuzF1ioA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjEyMDA4MCBTYWx0ZWRfXymnAldr5R7a/ 2nUbU5mGofmEhOTxeXf1ML1ghYu7t0vgDEcioDNmpJtWsjZ3zb/EA9YQ+uwF60vxDBCaUZlbIFX SdFW0+tnjubo1/uwBxKqwATLI74+wwRCLckNkWUD3fYwe1A4OWy3qi63y9Z/laf2qOvMKwyC0/V xHZ/h8Ia6Uy0T0/NCypwqnKqtiAm5f/Avo3Zc4E+NPZySQI4j/icwtEA+OgOtcS9b3whd/khk8E APmXapCqkBZHNinj2GxwrBExbrYhiDGwWo1rY4m8uc5EfEH3teU4+l6SOMZoYsLwAydQY/oFgXq C56Kn9JLtLze8cXtMZRYLLg0Agqop3ev95gRb5gxp86nMqeQslg+1Ovzc98Gv4mhpdo3w+KBQFP 0iw02O/EMkm9So2xu0BXA6mLmizZUpUhG88las8xO67ub82Z+BHXpWPfyRcFu9bq55PLQZJLMMU IZkHhdPeUPyjVQ4JJ/A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-12_03,2026-02-11_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 adultscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1011 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602120080 Add a node for the second TC9563 PCIe switch on PCIe1, which is connected in cascade to the first TC9563 switch via the former's downstream port. Two embedded Ethernet devices are present on one of the downstream ports of this second switch as well. All the ports present in the node represent the downstream ports and embedded endpoints. The second TC9563 is powered up via the same LDO regulators as the first one, and these can be controlled via two GPIOs, which are already present as fixed regulators. This TC9563 can also be configured through I2C. Signed-off-by: Sushrut Shree Trivedi Reviewed-by: Konrad Dybcio --- .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 105 +++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 +- 2 files changed, 106 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.= dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 0fb89e71bf7f..a8ccb9d8f6e2 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -153,6 +153,100 @@ pci@0,1 { }; }; =20 +&pcie1 { + iommu-map =3D <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x408 &apps_smmu 0x1c90 0x1>, + <0x410 &apps_smmu 0x1c91 0x1>, + <0x418 &apps_smmu 0x1c92 0x1>, + <0x500 &apps_smmu 0x1c93 0x1>, + <0x600 &apps_smmu 0x1c94 0x1>, + <0x700 &apps_smmu 0x1c95 0x1>, + <0x701 &apps_smmu 0x1c96 0x1>, + <0x800 &apps_smmu 0x1c97 0x1>, + <0x900 &apps_smmu 0x1c98 0x1>, + <0x901 &apps_smmu 0x1c99 0x1>; +}; + +&pcie1_switch0_dsp1 { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x30000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vdd_ntn_0p9>; + vdd18-supply =3D <&vdd_ntn_1p8>; + vdd09-supply =3D <&vdd_ntn_0p9>; + vddio1-supply =3D <&vdd_ntn_1p8>; + vddio2-supply =3D <&vdd_ntn_1p8>; + vddio18-supply =3D <&vdd_ntn_1p8>; + + i2c-parent =3D <&i2c1 0x33>; + + resx-gpios =3D <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie1_tc9563_resx_n>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x40800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x41000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x41800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + &tlmm { pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { pins =3D "gpio78"; @@ -163,4 +257,15 @@ pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { output-enable; power-source =3D <0>; }; + + pcie1_tc9563_resx_n: pcie1-tc9563-resx-state { + pins =3D "gpio124"; + function =3D "gpio"; + + bias-disable; + input-disable; + output-enable; + power-source =3D <0>; + }; + }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot= /dts/qcom/qcs6490-rb3gen2.dts index e3d2f01881ae..cd54525e45e0 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -852,7 +852,7 @@ pcie@0,0 { pinctrl-0 =3D <&tc9563_resx_n>; pinctrl-names =3D "default"; =20 - pcie@1,0 { + pcie1_switch0_dsp1: pcie@1,0 { reg =3D <0x20800 0x0 0x0 0x0 0x0>; #address-cells =3D <3>; #size-cells =3D <2>; --=20 2.25.1