From: Fangyu Yu <fangyu.yu@linux.alibaba.com>

This series adds support for two RISC-V IOMMU v1.0.1 invalidation extensions in
the RISC-V IOMMU driver:

  - Address Range Invalidation (capabilities.S), which allows encoding a NAPOT
    address range in the IOTINVAL.{VMA,GVMA} ADDR operand when the S bit is set,
    reducing the number of invalidation commands for large or superpage-backed
    mappings.

  - Non-leaf PTE Invalidation (capabilities.NL), which allows IOTINVAL.VMA with
    AV=1 and NL=1 to invalidate cached non-leaf PTE information for the given
    IOVA, addressing cases where updating mappings replaces a non-leaf entry.

Patch 1 introduces the missing capability/operand definitions and switches the
IOTLB invalidation path to use NAPOT range invalidations when supported.

Patch 2 adds the NL capability/operand definitions and extends the invalidation
path to optionally request non-leaf invalidation. When map_pages() replaces
non-leaf page-table entries, the driver invalidates the affected IOVA range with
non-leaf semantics.

No functional changes are expected on hardware that does not advertise these
capabilities; the driver continues to fall back to the existing invalidation
behavior.

Fangyu Yu (2):
  iommu/riscv: Add NAPOT range invalidation support for IOTINVAL
  iommu/riscv: Add non-leaf invalidation support

 drivers/iommu/riscv/iommu-bits.h |  17 +++++
 drivers/iommu/riscv/iommu.c      | 111 +++++++++++++++++++++++++++++--
 2 files changed, 124 insertions(+), 4 deletions(-)

-- 
2.50.1