From nobody Mon Feb 9 00:20:02 2026 Received: from out30-130.freemail.mail.aliyun.com (out30-130.freemail.mail.aliyun.com [115.124.30.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5247227FB05 for ; Sun, 8 Feb 2026 14:42:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770561750; cv=none; b=NHrLb02LAeFJEtFOQhswsuF/AUnKWUKVQhwIJU67g1HO+/znjFg9YvMNFMDYh37AG5Zf9FQdICVulQv2bpKUKjQ/MIIcoNazEwyREr7YgBuTk21YN0mVz72sMmEu9uxqsODew7sz2T4Sq9PxMxIjV4zPip42qIAzo64zjN869gM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770561750; c=relaxed/simple; bh=GTDJ3eRWXllECRowh3xafSUPTWf9JfmHXQtT+67Tpk0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hxJVEWbM8ER609DHvjE+DQWpiLz5LS8EXNqvkQegiwF8iU/e/oR2onP7O0lJOmf1n6fkeHvWMoyGXdn6g+dn7kyrYw7VJlWu6oWgiyEpLehGgemEPkz+BQb06eD0NOeaR28kNRnJI2bFhoy98Uz5zW3AvmdfTp+I029YePxlMt0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=SSIeIILP; arc=none smtp.client-ip=115.124.30.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="SSIeIILP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1770561746; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=832YTHZrK3Pyq+HUnUx8cNLTvYiKXNSGu9dxfufivbw=; b=SSIeIILPO6mhhcIFMXrELRMQb/LJZP83XIL6i4U2ujvtM7inJtkHMjr8qbni7uICsgz3N7035SQiOB2C31pIEBeB4nkPwYgt3UmlcmcSHPRrRnpQGIsS5XUQxnFUK9GRcuPB4SrLDcPg9enOsNpHw4xKUEs5X2UvnxgtRnvoQe0= Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0WylHpCX_1770561742 cluster:ay36) by smtp.aliyun-inc.com; Sun, 08 Feb 2026 22:42:25 +0800 From: fangyu.yu@linux.alibaba.com To: tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, andrew.jones@oss.qualcomm.com Cc: guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Fangyu Yu Subject: [PATCH 1/2] iommu/riscv: Add NAPOT range invalidation support for IOTINVAL Date: Sun, 8 Feb 2026 22:42:12 +0800 Message-Id: <20260208144213.94856-2-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260208144213.94856-1-fangyu.yu@linux.alibaba.com> References: <20260208144213.94856-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu RISC-V IOMMU v1.0.1 defines an Address Range Invalidation extension (capabilities.S) which allows encoding the invalidation size as a NAPOT range in the ADDR operand when issuing IOTINVAL.VMA/GVMA with the S bit set. This can significantly reduce the number of invalidation commands, especially when superpages are used. Add the missing capabilities.S definition, introduce the IOTINVAL.S bit and a helper to program NAPOT-encoded ranges, and switch the IOTLB invalidation path to use range invalidations when it is available. The implementation splits the requested interval into the largest aligned NAPOT ranges and falls back to whole address space invalidation for larger ranges. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu-bits.h | 10 ++++ drivers/iommu/riscv/iommu.c | 86 ++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-b= its.h index 98daf0e1a306..0d1f8813ae31 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -62,6 +62,7 @@ #define RISCV_IOMMU_CAPABILITIES_PD8 BIT_ULL(38) #define RISCV_IOMMU_CAPABILITIES_PD17 BIT_ULL(39) #define RISCV_IOMMU_CAPABILITIES_PD20 BIT_ULL(40) +#define RISCV_IOMMU_CAPABILITIES_S BIT_ULL(43) =20 /** * enum riscv_iommu_igs_settings - Interrupt Generation Support Settings @@ -472,6 +473,7 @@ struct riscv_iommu_command { #define RISCV_IOMMU_CMD_IOTINVAL_PSCV BIT_ULL(32) #define RISCV_IOMMU_CMD_IOTINVAL_GV BIT_ULL(33) #define RISCV_IOMMU_CMD_IOTINVAL_GSCID GENMASK_ULL(59, 44) +#define RISCV_IOMMU_CMD_IOTINVAL_S BIT_ULL(9) /* dword1[61:10] is the 4K-aligned page address */ #define RISCV_IOMMU_CMD_IOTINVAL_ADDR GENMASK_ULL(61, 10) =20 @@ -715,6 +717,14 @@ static inline void riscv_iommu_cmd_inval_vma(struct ri= scv_iommu_command *cmd) cmd->dword1 =3D 0; } =20 +static inline void riscv_iommu_cmd_inval_set_range(struct riscv_iommu_comm= and *cmd, + u64 addr) +{ + cmd->dword1 =3D FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, addr) | + RISCV_IOMMU_CMD_IOTINVAL_S; + cmd->dword0 |=3D RISCV_IOMMU_CMD_IOTINVAL_AV; +} + static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_comma= nd *cmd, u64 addr) { diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index d9429097a2b5..ae48409a052a 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -913,7 +913,88 @@ static void riscv_iommu_bond_unlink(struct riscv_iommu= _domain *domain, riscv_iommu_cmd_sync(iommu, RISCV_IOMMU_IOTINVAL_TIMEOUT); } } +/* + * Encode a NAPOT range for IOTINVAL.{VMA,GVMA} when the S bit is set. + * + * Per RISC-V IOMMU Address Range Invalidation Extension: + * - The ADDR operand is NAPOT encoded in 4KiB units. + * - Scanning ADDR from bit 0 upwards, if the first 0 bit is at position= X, + * the invalidation range size is 2^(X+1) * 4KiB (X=3D0 =3D> 8KiB). + * - Thus, for a range of size =3D 4KiB * 2^k (k >=3D 1), the encoded AD= DR has + * its low (k-1) bits set to 1, and bit (k-1) cleared (by alignment). + * + */ +static unsigned long range_encode(unsigned long start, unsigned long size) +{ + unsigned long blocks =3D size >> PAGE_SHIFT; + unsigned long x =3D ilog2(blocks) - 1; + + return (start >> PAGE_SHIFT) | ((1ULL << x) - 1); +} +static void riscv_iommu_iotlb_inval_range(struct riscv_iommu_domain *domai= n, + struct riscv_iommu_device *iommu, + unsigned long start, unsigned long end) +{ + struct riscv_iommu_command cmd; + unsigned long len =3D end - start + 1; + unsigned long page_start, limit, cur, max_range, size, range_addr; + int order; + + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid); + + /* + * Using NAPOT range invalidations may still require multiple commands + * to cover a large interval (e.g. when the range is poorly aligned and + * needs to be split into many smaller NAPOT blocks). + * + * To keep the number of queued IOTINVAL commands bounded and avoid + * excessive invalidation overhead, treat very large invalidation + * requests as a global flush for the address space (AV=3D0, PSCV=3D1). + * + */ + if (len > SZ_1G) { + riscv_iommu_cmd_send(iommu, &cmd); + return; + } =20 + page_start =3D start & PAGE_MASK; + limit =3D PAGE_ALIGN(end + 1); + cur =3D page_start; + + while (cur < limit) { + max_range =3D 0; + + /* + * We cap the maximum NAPOT range to 1GiB (order=3D18, i.e. 2^18 * 4KiB)= and + * fall back to a whole-address-space invalidation for larger ranges. Th= is + * keeps the command generation bounded and aligns with the existing pol= icy + * of treating very large invalidations as global flushes. + */ + for (order =3D 18; order >=3D 1; order--) { + /* 1GB, ... , 16KB, 8KB */ + size =3D (1ULL << order) * SZ_4K; + if (cur + size <=3D limit && IS_ALIGNED(cur, size)) { + max_range =3D size; + break; + } + } + + if (max_range) { + range_addr =3D range_encode(cur, max_range); + + riscv_iommu_cmd_inval_set_range(&cmd, range_addr); + riscv_iommu_cmd_send(iommu, &cmd); + cur +=3D max_range; + continue; + } + + /* Fall back to single-page invalidation */ + riscv_iommu_cmd_inval_set_addr(&cmd, cur); + riscv_iommu_cmd_send(iommu, &cmd); + cur +=3D PAGE_SIZE; + } +} /* * Send IOTLB.INVAL for whole address space for ranges larger than 2MB. * This limit will be replaced with range invalidations, if supported by @@ -970,6 +1051,11 @@ static void riscv_iommu_iotlb_inval(struct riscv_iomm= u_domain *domain, if (iommu =3D=3D prev) continue; =20 + if (!!(iommu->caps & RISCV_IOMMU_CAPABILITIES_S)) { + riscv_iommu_iotlb_inval_range(domain, iommu, start, end); + continue; + } + riscv_iommu_cmd_inval_vma(&cmd); riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid); if (len && len < RISCV_IOMMU_IOTLB_INVAL_LIMIT) { --=20 2.50.1 From nobody Mon Feb 9 00:20:02 2026 Received: from out30-124.freemail.mail.aliyun.com (out30-124.freemail.mail.aliyun.com [115.124.30.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 087A427FB05 for ; Sun, 8 Feb 2026 14:42:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770561760; cv=none; b=paW9lxwDISzrp4aG4YsSMODQzRar2v2qgJO5uNSjD8amYfNXIBoNFvPV6copoLIDhk8YynsecQO0iUFRFAdJ09QzKgvPdxDDlzR8vuYgl6TzJWeV0K6LXSin8H/N+ItfLmw3TC7/HEy32b97YfF4PNYWSJtOllHkepfie6XIEOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770561760; c=relaxed/simple; bh=Df6xI1i0LwF6dItD+EnIg+S7lMjydVSa2v73XfQ3nrA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XKe3WwVXCyn6YCFZCUayqrN0GODcQU+Q1/9FWwKZENyjsoMunguhA/g5ZZn3KhCzVK+XZCt5YwVjFpz0utljkzGEl8bVKpxeIf/Z5TNFSozC0PcB8FJ63wAFBtmE1DcO+vdcDwt65c+Xld3mFQSNHWUMLXKNx2ZoMvenRoxGllw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=I4zc9glz; arc=none smtp.client-ip=115.124.30.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="I4zc9glz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1770561749; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=a7cRGNrOwnSEMVTnWHlQkoIS4hluf6bSkDbchWo+rq0=; b=I4zc9glz993ScxZsHG6SFQ9wVUGceSnMTCSF0TySNQ6Knp5hX6xTl9SvWYoceZXQ01PLJ1RevM87ZfGhUjGa7wM/IPbXv+wGNGniy3ntOL2uN0aKCK0aaR0Na0Fid5yaa85sBIGMOWKoSmWZZKRCkAQZ5T9TY+s9Xw1mMkgNCXk= Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0WylHpD3_1770561745 cluster:ay36) by smtp.aliyun-inc.com; Sun, 08 Feb 2026 22:42:27 +0800 From: fangyu.yu@linux.alibaba.com To: tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, andrew.jones@oss.qualcomm.com Cc: guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Fangyu Yu Subject: [PATCH 2/2] iommu/riscv: Add non-leaf invalidation support Date: Sun, 8 Feb 2026 22:42:13 +0800 Message-Id: <20260208144213.94856-3-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260208144213.94856-1-fangyu.yu@linux.alibaba.com> References: <20260208144213.94856-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu The RISC-V IOMMU v1.0.1 spec adds the Non-leaf PTE Invalidation extension (capabilities.NL) which allows IOTINVAL.VMA to invalidate cached non-leaf PTE information when performing address-specific invalidations. Add the NL capability bit definition and the IOTINVAL.VMA NL operand bit, and provide a helper to set NL in an invalidation command. Extend the internal IOTLB invalidation helpers to optionally request non- leaf invalidation and, when mapping replaces non-leaf page-table entries (freelist is not empty), invalidate the affected IOVA range with non-leaf semantics instead of falling back to invalidate-all. This reduces the scope of invalidations while keeping compatibility with implementations that do not support the NL extension. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu-bits.h | 7 +++++++ drivers/iommu/riscv/iommu.c | 29 +++++++++++++++++++++++------ 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-b= its.h index 0d1f8813ae31..35bb9eaa5214 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -62,6 +62,7 @@ #define RISCV_IOMMU_CAPABILITIES_PD8 BIT_ULL(38) #define RISCV_IOMMU_CAPABILITIES_PD17 BIT_ULL(39) #define RISCV_IOMMU_CAPABILITIES_PD20 BIT_ULL(40) +#define RISCV_IOMMU_CAPABILITIES_NL BIT_ULL(42) #define RISCV_IOMMU_CAPABILITIES_S BIT_ULL(43) =20 /** @@ -473,6 +474,7 @@ struct riscv_iommu_command { #define RISCV_IOMMU_CMD_IOTINVAL_PSCV BIT_ULL(32) #define RISCV_IOMMU_CMD_IOTINVAL_GV BIT_ULL(33) #define RISCV_IOMMU_CMD_IOTINVAL_GSCID GENMASK_ULL(59, 44) +#define RISCV_IOMMU_CMD_IOTINVAL_NL BIT_ULL(34) #define RISCV_IOMMU_CMD_IOTINVAL_S BIT_ULL(9) /* dword1[61:10] is the 4K-aligned page address */ #define RISCV_IOMMU_CMD_IOTINVAL_ADDR GENMASK_ULL(61, 10) @@ -732,6 +734,11 @@ static inline void riscv_iommu_cmd_inval_set_addr(stru= ct riscv_iommu_command *cm cmd->dword0 |=3D RISCV_IOMMU_CMD_IOTINVAL_AV; } =20 +static inline void riscv_iommu_cmd_inval_set_nonleaf(struct riscv_iommu_co= mmand *cmd) +{ + cmd->dword0 |=3D RISCV_IOMMU_CMD_IOTINVAL_NL; +} + static inline void riscv_iommu_cmd_inval_set_pscid(struct riscv_iommu_comm= and *cmd, int pscid) { diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index ae48409a052a..acc82c8626ce 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -933,7 +933,8 @@ static unsigned long range_encode(unsigned long start, = unsigned long size) } static void riscv_iommu_iotlb_inval_range(struct riscv_iommu_domain *domai= n, struct riscv_iommu_device *iommu, - unsigned long start, unsigned long end) + unsigned long start, unsigned long end, + bool non_leaf) { struct riscv_iommu_command cmd; unsigned long len =3D end - start + 1; @@ -962,6 +963,16 @@ static void riscv_iommu_iotlb_inval_range(struct riscv= _iommu_domain *domain, limit =3D PAGE_ALIGN(end + 1); cur =3D page_start; =20 + if (non_leaf) { + if (!!(iommu->caps & RISCV_IOMMU_CAPABILITIES_NL)) { + riscv_iommu_cmd_inval_set_nonleaf(&cmd); + } else { + /* Falls back to whole address space invalidation */ + riscv_iommu_cmd_send(iommu, &cmd); + return; + } + } + while (cur < limit) { max_range =3D 0; =20 @@ -1004,7 +1015,8 @@ static void riscv_iommu_iotlb_inval_range(struct risc= v_iommu_domain *domain, #define RISCV_IOMMU_IOTLB_INVAL_LIMIT (2 << 20) =20 static void riscv_iommu_iotlb_inval(struct riscv_iommu_domain *domain, - unsigned long start, unsigned long end) + unsigned long start, unsigned long end, + bool non_leaf) { struct riscv_iommu_bond *bond; struct riscv_iommu_device *iommu, *prev; @@ -1052,8 +1064,11 @@ static void riscv_iommu_iotlb_inval(struct riscv_iom= mu_domain *domain, continue; =20 if (!!(iommu->caps & RISCV_IOMMU_CAPABILITIES_S)) { - riscv_iommu_iotlb_inval_range(domain, iommu, start, end); + riscv_iommu_iotlb_inval_range(domain, iommu, start, end, non_leaf); continue; + } else if (non_leaf) { + /* Falls back to whole address space invalidation */ + len =3D ULONG_MAX; } =20 riscv_iommu_cmd_inval_vma(&cmd); @@ -1155,7 +1170,7 @@ static void riscv_iommu_iotlb_flush_all(struct iommu_= domain *iommu_domain) { struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); =20 - riscv_iommu_iotlb_inval(domain, 0, ULONG_MAX); + riscv_iommu_iotlb_inval(domain, 0, ULONG_MAX, false); } =20 static void riscv_iommu_iotlb_sync(struct iommu_domain *iommu_domain, @@ -1163,7 +1178,7 @@ static void riscv_iommu_iotlb_sync(struct iommu_domai= n *iommu_domain, { struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); =20 - riscv_iommu_iotlb_inval(domain, gather->start, gather->end); + riscv_iommu_iotlb_inval(domain, gather->start, gather->end, false); } =20 #define PT_SHIFT (PAGE_SHIFT - ilog2(sizeof(pte_t))) @@ -1284,6 +1299,7 @@ static int riscv_iommu_map_pages(struct iommu_domain = *iommu_domain, unsigned long pte, old, pte_prot; int rc =3D 0; struct iommu_pages_list freelist =3D IOMMU_PAGES_LIST_INIT(freelist); + unsigned long inval_start =3D iova; =20 if (!(prot & IOMMU_WRITE)) pte_prot =3D _PAGE_BASE | _PAGE_READ; @@ -1322,7 +1338,8 @@ static int riscv_iommu_map_pages(struct iommu_domain = *iommu_domain, * This will be updated with hardware support for * capability.NL (non-leaf) IOTINVAL command. */ - riscv_iommu_iotlb_inval(domain, 0, ULONG_MAX); + riscv_iommu_iotlb_inval(domain, inval_start, + inval_start + size - 1, true); iommu_put_pages_list(&freelist); } =20 --=20 2.50.1