Hi I2C and HWMON maintainers,

Intel i801 SMBus controllers feature a "SPD Write Disable" bit 
in the SMBHSTCFG register. When set by firmware, the hardware 
silently blocks all write transactions to the SPD EEPROM 
address range (0x50-0x57) while allowing reads to succeed.

This creates a significant issue for the spd5118 hwmon driver. 
The SPD5118 requires write access for switching between 
register pages to read temperature data, and for cache 
synchronization during suspend/resume. When SPD Write Disable 
is set and the spd5118 driver attempts write transactions, the 
bus will generate a storm of SMBus DEV_ERR messages.

This patch series proposes a generic solution by:
1. Introducing a new adapter quirk flag in include/linux/i2c.h 
to communicate this hardware restriction.
2. Modifying drivers/i2c/i2c-i801.c to detect the SPD Write 
Disable bit and set the quirk flag.
3. Modifying drivers/hwmon/spd5118.c to check for this quirk 
during probe and fail cleanly, as write access is mandatory.

By using this mechanism, we avoid embedding device-specific 
policies in the controller driver and provide client drivers 
with the necessary information to make an informed decision.

Tinsae Tadesse (2):
  i2c: i801: Detect SPD Write Disable and expose as adapter quirk
  hwmon: spd5118: Fail probe if SPD writes are disabled

 drivers/hwmon/spd5118.c       | 15 +++++++++++++++
 drivers/i2c/busses/i2c-i801.c | 16 +++++++++++++++-
 include/linux/i2c.h           |  3 +++
 3 files changed, 33 insertions(+), 1 deletion(-)

-- 
2.52.0