From: Heiko Stuebner <heiko.stuebner@cherry.de>

Using a combination of fixed clock and gpio-gate clock works but does
not describe the actual hardware. Use the gated-fixed-clock binding
to describe this in a nicer way.

Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
---
 arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
index 952affaf455c..6eea4e0b6ca4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
@@ -90,21 +90,16 @@ led-1 {
 	 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
 	 * clock generator.
 	 * The clock output is gated via the OE pin on the clock generator.
-	 * This is modeled as a fixed-clock plus a gpio-gate-clock.
 	 */
-	pcie_refclk_gen: pcie-refclk-gen-clock {
-		compatible = "fixed-clock";
+	pcie_refclk: pcie-clock-generator {
+		compatible = "gated-fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <100000000>;
-	};
-
-	pcie_refclk: pcie-refclk-clock {
-		compatible = "gpio-gate-clock";
-		clocks = <&pcie_refclk_gen>;
-		#clock-cells = <0>;
+		clock-output-names = "pcie3_refclk";
 		enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
 		pinctrl-names = "default";
 		pinctrl-0 = <&pcie30x4_clkreqn_m0>;
+		vdd-supply = <&vcca_3v3_s0>;
 	};
 
 	pps {
-- 
2.47.2

Hi Heiko,

On 2/5/26 11:21 AM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@cherry.de>
> 
> Using a combination of fixed clock and gpio-gate clock works but does
> not describe the actual hardware. Use the gated-fixed-clock binding
> to describe this in a nicer way.
> 

You also add a regulator as supply :)

> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
> ---
>   arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 13 ++++---------
>   1 file changed, 4 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
> index 952affaf455c..6eea4e0b6ca4 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
> @@ -90,21 +90,16 @@ led-1 {
>   	 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
>   	 * clock generator.
>   	 * The clock output is gated via the OE pin on the clock generator.
> -	 * This is modeled as a fixed-clock plus a gpio-gate-clock.
>   	 */

I'm assuming the whole comment can be removed as it was just the 
reasoning behind two clocks and now we only have one which is pretty 
self explanatory?

> -	pcie_refclk_gen: pcie-refclk-gen-clock {
> -		compatible = "fixed-clock";
> +	pcie_refclk: pcie-clock-generator {
> +		compatible = "gated-fixed-clock";
>   		#clock-cells = <0>;
>   		clock-frequency = <100000000>;
> -	};
> -
> -	pcie_refclk: pcie-refclk-clock {
> -		compatible = "gpio-gate-clock";
> -		clocks = <&pcie_refclk_gen>;
> -		#clock-cells = <0>;
> +		clock-output-names = "pcie3_refclk";

Why change the name? I'm also wondering if we cannot have free backward 
compatibility by setting this to pcie-refclk-clock to match the old name?

Same remarks for Tiger (patch 2).

Change looks fine though.

Cheers,
Quentin