From: Biju Das <biju.das.jz@bp.renesas.com>
As per the RZ/G3L Hardware manual, CPG_CLKON_ETH register bits{12,13} are
to control the RMII{tx, rx} clocks. Document the RMII{tx, rx} clocks for
RZ/G3L SoC.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Fixes: 3ac2aa31b489eb4e ("dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/G3L SoC")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Collected tag
* Added Fixes tag
* Fixed typo {tx.rx}->{tx, rx} in xommit description.
---
.../devicetree/bindings/net/renesas,rzv2h-gbeth.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
index fb60f745a1ff..2125b5ddf73d 100644
--- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
@@ -58,6 +58,8 @@ properties:
- description: TX clock phase-shifted by 180 degrees
- description: RX clock phase-shifted by 180 degrees
- description: RMII clock
+ - description: RMII TX clock
+ - description: RMII RX clock
minItems: 7
@@ -77,6 +79,8 @@ properties:
- const: tx-180
- const: rx-180
- const: rmii
+ - const: rmii_tx
+ - const: rmii_rx
minItems: 7
@@ -170,10 +174,10 @@ allOf:
then:
properties:
clocks:
- minItems: 8
+ minItems: 10
clock-names:
- minItems: 8
+ minItems: 10
interrupts:
minItems: 15
--
2.43.0