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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Date: Wed, 4 Feb 2026 21:25:38 +0000 Message-ID: <20260204212541.4870-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das As per the RZ/G3L Hardware manual, CPG_CLKON_ETH register bits{12,13} are to control the RMII{tx, rx} clocks. Document the RMII{tx, rx} clocks for RZ/G3L SoC. Acked-by: Conor Dooley Fixes: 3ac2aa31b489eb4e ("dt-bindings: net: renesas,rzv2h-gbeth: Document R= enesas RZ/G3L SoC") Signed-off-by: Biju Das --- v1->v2: * Collected tag * Added Fixes tag * Fixed typo {tx.rx}->{tx, rx} in xommit description. --- .../devicetree/bindings/net/renesas,rzv2h-gbeth.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml= b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index fb60f745a1ff..2125b5ddf73d 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -58,6 +58,8 @@ properties: - description: TX clock phase-shifted by 180 degrees - description: RX clock phase-shifted by 180 degrees - description: RMII clock + - description: RMII TX clock + - description: RMII RX clock =20 minItems: 7 =20 @@ -77,6 +79,8 @@ properties: - const: tx-180 - const: rx-180 - const: rmii + - const: rmii_tx + - const: rmii_rx =20 minItems: 7 =20 @@ -170,10 +174,10 @@ allOf: then: properties: clocks: - minItems: 8 + minItems: 10 =20 clock-names: - minItems: 8 + minItems: 10 =20 interrupts: minItems: 15 --=20 2.43.0