.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 234 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +- 2 files changed, 240 insertions(+), 6 deletions(-)
Add nodes for the two additional TC9563 PCIe switches present on the
QCOM RB3Gen2 Industrial Mezzanine platform.
One of the TC9563 is connected directly to the PCIe0 root-port while
the second TC9563 switch is connected in cascade fashion to another
already available TC9563 switch on PCIe1 via the former's downstream
port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
would look something like below:
┌────────────────────────────┐
│ │
│ │
│ │
│ SoC │
│ │
│ PCIe0 PCIe1 │
│ ┌───┐ ┌───┐ │
└────└─┬─┘───────────└─┬─┘───┘
│ │
│ │
│ │
┌────────────────┘ └────────────────┐
│ │
│ │
│ │
┌────────┴─────────┐ ┌──────────┴───────┐
│ USP │ │ USP │
│ │ │ │
│ TC9563 │ │ TC9563 │
│ │ │ │
│ │ │ │
│ DSP1 DSP2 DSP3 │ │ DSP1 DSP2 DSP3 │
└──┬──────┬─────┬──┘ └───┬─────┬─────┬──┘
│ │ │ │ │ │
│ │ │ │ │ │
│ │ │ │ │ │
│ │ │ │ EP ETHERNET
│ │ │ │
│ │ │ └──────┐
EP EP ETHERNET │
│
│
┌─────────┴────────┐
│ USP │
│ │
│ TC9563 │
│ │
│ │
│ DSP1 DSP2 DSP3 │
└──┬──────┬─────┬──┘
│ │ │
│ │ │
│ │ │
│ │ │
│ │ │
EP EP ETHERNET
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
Changes in v2:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v1: https://lore.kernel.org/r/20260131-industrial-mezzanine-pcie-v1-0-b3c2905dd768@oss.qualcomm.com
---
Sushrut Shree Trivedi (2):
arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 234 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +-
2 files changed, 240 insertions(+), 6 deletions(-)
---
base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2
change-id: 20260131-industrial-mezzanine-pcie-75dd851f5b04
Best regards,
--
Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
On Tue, Feb 03, 2026 at 10:01:27AM +0530, Sushrut Shree Trivedi wrote: > Add nodes for the two additional TC9563 PCIe switches present on the > QCOM RB3Gen2 Industrial Mezzanine platform. > > One of the TC9563 is connected directly to the PCIe0 root-port while > the second TC9563 switch is connected in cascade fashion to another > already available TC9563 switch on PCIe1 via the former's downstream > port (DSP). The final PCIe hierarchy on the Industrial Mezz platform > would look something like below: > > --- > Changes in v2: > - EDITME: describe what is new in this series revision. > - EDITME: use bulletpoints and terse descriptions. The b4 tool should have warned you about this. Why was it ignored? Where is the changelog? > - Link to v1: https://lore.kernel.org/r/20260131-industrial-mezzanine-pcie-v1-0-b3c2905dd768@oss.qualcomm.com > > --- > Sushrut Shree Trivedi (2): > arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 > arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 > > .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 234 +++++++++++++++++++++ > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +- > 2 files changed, 240 insertions(+), 6 deletions(-) > --- > base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2 > change-id: 20260131-industrial-mezzanine-pcie-75dd851f5b04 > > Best regards, > -- > Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> > -- With best wishes Dmitry
On Tue, 03 Feb 2026 10:01:27 +0530, Sushrut Shree Trivedi wrote:
> Add nodes for the two additional TC9563 PCIe switches present on the
> QCOM RB3Gen2 Industrial Mezzanine platform.
>
> One of the TC9563 is connected directly to the PCIe0 root-port while
> the second TC9563 switch is connected in cascade fashion to another
> already available TC9563 switch on PCIe1 via the former's downstream
> port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
> would look something like below:
>
> ┌────────────────────────────┐
> │ │
> │ │
> │ │
> │ SoC │
> │ │
> │ PCIe0 PCIe1 │
> │ ┌───┐ ┌───┐ │
> └────└─┬─┘───────────└─┬─┘───┘
> │ │
> │ │
> │ │
> ┌────────────────┘ └────────────────┐
> │ │
> │ │
> │ │
> ┌────────┴─────────┐ ┌──────────┴───────┐
> │ USP │ │ USP │
> │ │ │ │
> │ TC9563 │ │ TC9563 │
> │ │ │ │
> │ │ │ │
> │ DSP1 DSP2 DSP3 │ │ DSP1 DSP2 DSP3 │
> └──┬──────┬─────┬──┘ └───┬─────┬─────┬──┘
> │ │ │ │ │ │
> │ │ │ │ │ │
> │ │ │ │ │ │
> │ │ │ │ EP ETHERNET
> │ │ │ │
> │ │ │ └──────┐
> EP EP ETHERNET │
> │
> │
> ┌─────────┴────────┐
> │ USP │
> │ │
> │ TC9563 │
> │ │
> │ │
> │ DSP1 DSP2 DSP3 │
> └──┬──────┬─────┬──┘
> │ │ │
> │ │ │
> │ │ │
> │ │ │
> │ │ │
> EP EP ETHERNET
>
>
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
> Changes in v2:
> - EDITME: describe what is new in this series revision.
> - EDITME: use bulletpoints and terse descriptions.
> - Link to v1: https://lore.kernel.org/r/20260131-industrial-mezzanine-pcie-v1-0-b3c2905dd768@oss.qualcomm.com
>
> ---
> Sushrut Shree Trivedi (2):
> arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
> arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
>
> .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 234 +++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +-
> 2 files changed, 240 insertions(+), 6 deletions(-)
> ---
> base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2
> change-id: 20260131-industrial-mezzanine-pcie-75dd851f5b04
>
> Best regards,
> --
> Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>
>
>
My bot found DTB warnings on the .dts/.dtsi files added or changed in
this series.
Some warnings may be existing warnings. Consider fixing existing
warnings before adding new features.
Perhaps the warnings are fixed by another series. If that is the case,
please set the base commit and any dependencies for the series using
"b4".
Ultimately, it is up to the platform maintainer whether these warnings
are acceptable or not.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: 4f938c7d3b25d87b356af4106c2682caf8c835a2 (use --merge-base to override)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20260203-industrial-mezzanine-pcie-v2-0-8579ed6bf931@oss.qualcomm.com:
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:86.3-35: Warning (reg_format): /fragment@4/__overlay__/pcie@0,0:reg: property has invalid length (20 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:171.3-35: Warning (reg_format): /fragment@6/__overlay__/pcie@0,0:reg: property has invalid length (20 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:91.3-10: Warning (ranges_format): /fragment@4/__overlay__/pcie@0,0:ranges: empty "ranges" property but its #address-cells (3) differs from /fragment@4/__overlay__ (2)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:91.3-10: Warning (ranges_format): /fragment@4/__overlay__/pcie@0,0:ranges: empty "ranges" property but its #size-cells (2) differs from /fragment@4/__overlay__ (1)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:176.3-10: Warning (ranges_format): /fragment@6/__overlay__/pcie@0,0:ranges: empty "ranges" property but its #address-cells (3) differs from /fragment@6/__overlay__ (2)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:176.3-10: Warning (ranges_format): /fragment@6/__overlay__/pcie@0,0:ranges: empty "ranges" property but its #size-cells (2) differs from /fragment@6/__overlay__ (1)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtbo: Warning (pci_device_reg): Failed prerequisite 'reg_format'
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtbo: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtbo: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtbo: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:84.30-146.4: Warning (avoid_default_addr_size): /fragment@4/__overlay__/pcie@0,0: Relying on default #address-cells value
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:84.30-146.4: Warning (avoid_default_addr_size): /fragment@4/__overlay__/pcie@0,0: Relying on default #size-cells value
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:169.30-231.4: Warning (avoid_default_addr_size): /fragment@6/__overlay__/pcie@0,0: Relying on default #address-cells value
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:169.30-231.4: Warning (avoid_default_addr_size): /fragment@6/__overlay__/pcie@0,0: Relying on default #size-cells value
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dtb: pmic@2 (qcom,pm8350c): pwm:nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dtb: pwm (qcom,pm8350c-pwm): nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0:pci@0,1: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0:pci@0,0: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'device_type', 'pci@0,0', 'pci@0,1', 'ranges', 'reg' were unexpected)
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@3,0: pci@0,1: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@3,0: pci@0,0: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0:pci@0,1: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0:pci@0,0: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'device_type', 'pci@0,0', 'pci@0,1', 'ranges', 'reg' were unexpected)
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@3,0: pci@0,1: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@3,0: pci@0,0: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pmic@2 (qcom,pm8350c): pwm:nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pwm (qcom,pm8350c-pwm): nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtb: pmic@2 (qcom,pm8350c): pwm:nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtb: pwm (qcom,pm8350c-pwm): nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml
Hi, Apologies for the error, this is v1 series. Thanks On 2/3/2026 10:01 AM, Sushrut Shree Trivedi wrote: > Add nodes for the two additional TC9563 PCIe switches present on the > QCOM RB3Gen2 Industrial Mezzanine platform. > > One of the TC9563 is connected directly to the PCIe0 root-port while > the second TC9563 switch is connected in cascade fashion to another > already available TC9563 switch on PCIe1 via the former's downstream > port (DSP). The final PCIe hierarchy on the Industrial Mezz platform > would look something like below: > > ┌────────────────────────────┐ > │ │ > │ │ > │ │ > │ SoC │ > │ │ > │ PCIe0 PCIe1 │ > │ ┌───┐ ┌───┐ │ > └────└─┬─┘───────────└─┬─┘───┘ > │ │ > │ │ > │ │ > ┌────────────────┘ └────────────────┐ > │ │ > │ │ > │ │ > ┌────────┴─────────┐ ┌──────────┴───────┐ > │ USP │ │ USP │ > │ │ │ │ > │ TC9563 │ │ TC9563 │ > │ │ │ │ > │ │ │ │ > │ DSP1 DSP2 DSP3 │ │ DSP1 DSP2 DSP3 │ > └──┬──────┬─────┬──┘ └───┬─────┬─────┬──┘ > │ │ │ │ │ │ > │ │ │ │ │ │ > │ │ │ │ │ │ > │ │ │ │ EP ETHERNET > │ │ │ │ > │ │ │ └──────┐ > EP EP ETHERNET │ > │ > │ > ┌─────────┴────────┐ > │ USP │ > │ │ > │ TC9563 │ > │ │ > │ │ > │ DSP1 DSP2 DSP3 │ > └──┬──────┬─────┬──┘ > │ │ │ > │ │ │ > │ │ │ > │ │ │ > │ │ │ > EP EP ETHERNET > > > > Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> > --- > Changes in v2: > - EDITME: describe what is new in this series revision. > - EDITME: use bulletpoints and terse descriptions. > - Link to v1: https://lore.kernel.org/r/20260131-industrial-mezzanine-pcie-v1-0-b3c2905dd768@oss.qualcomm.com > > --- > Sushrut Shree Trivedi (2): > arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 > arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 > > .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 234 +++++++++++++++++++++ > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +- > 2 files changed, 240 insertions(+), 6 deletions(-) > --- > base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2 > change-id: 20260131-industrial-mezzanine-pcie-75dd851f5b04 > > Best regards,
On 2/3/26 5:37 AM, Sushrut Shree Trivedi wrote: > Hi, > > Apologies for the error, this is v1 series. Please make sure to send the next revision as v3, so that the tools don't get confused by seeing two 'v2's Konrad
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