From nobody Mon Feb 9 19:43:04 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42C2F7263B for ; Tue, 3 Feb 2026 04:31:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770093102; cv=none; b=Oymeub8pAto8thVTz72BsTeH0Ij0m90bWVtilckK6YAXgDvku7mx8ijqZXsKGCxQ9v0MZaibBfAjxS4N/Wk1MEJCArXrih3UQaHPlFOQMZgDWdcfvYDLMSYbx07Q/GHCMVdMgrKlx6zrm/WuWgSVOvxeHm85Iym42dJoxkYm7Zw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770093102; c=relaxed/simple; bh=9mk67q2Nm7U9N4K8hxF/WDuU5gSRnJaaKjFBP7XeR7A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bdGOriVI1eMACa5UuPHja51ebkeLHiYbIrTTo/LqH6jh4Xrip5VVM06eLtTTNuhqJKDCaluz4j8jFW6ri4H78vZHtHDmQoFsuhHZUMlPg3E7Nu3W00MRPqC0EU6t8u0mPuxCmV2aEXADj9qeKeycd6m1FaGuQoZJD6GwEpmeA9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=FArgaFMK; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Tubx90pn; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="FArgaFMK"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Tubx90pn" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6134AiJH571041 for ; Tue, 3 Feb 2026 04:31:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 7q3JrJvoZ71ljdPa5eU6lAaROQA6xQR58WcgdDtxkw4=; b=FArgaFMK9Qjlf77g DYfofZzr29wk++HfSoN9rwmP0sgJufPG5W1vOZhnTVh7CGph+9PYdvjxas26Bmmc Hf19+Mlx5wRYZo591dNxshCst+FPsExRq07DF8Rz9ptGfoVjPT2rDiOfnqNDeOfs BTyXgW1kVq0BqJZKwCmI88WQpaOqSe2kedSxspcl6XUVTFPfp7o2TdYBZvfrBOlb TcsYYQKxx6kBnY0uOpfP2moJ3HQxvkfG1IyOPt2LQcYeUWeDOZM6o/9QlrSs0b56 Z6FNX6dOwLZbDK7YfK0mTrfIKM+/q2tB73dR3z3fb6wmLydsTpeNcxOk/9dgJDF6 YBe0ng== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c2tkmjvmf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 03 Feb 2026 04:31:39 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-29f1f79d6afso58041035ad.0 for ; Mon, 02 Feb 2026 20:31:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1770093099; x=1770697899; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7q3JrJvoZ71ljdPa5eU6lAaROQA6xQR58WcgdDtxkw4=; b=Tubx90pnkihXLKT9gfscBMsm9io2xfo5VYEDG3qYxRgzkD5xZMu6L3zqq/bZLQ2yQN 96B5JeyuSGdRhHYsL3AF6aBlYP/pVIUC9WErFxHgb4wZ7OXHVbuW8SM1MPZDPpEMeKHr BUpOE9pNHUQkkgNL86TYIIdFl68NZW6cR+6MlDyItQUhRSftfuM2LCvmfZnethg9SIqw wPQro1bUdzHwNcLztzIRYjNu99mEI1NiyN7YsbSN0+mYpIcgqyMFvCgeqjhtqOyCrLUU hxks4QDbB/FP9RVkapeLzaXFFwJa6aD2u0GlNcXaMMbeE4s/J5pF2k4dX7WD7qHu/nu+ 1U0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770093099; x=1770697899; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7q3JrJvoZ71ljdPa5eU6lAaROQA6xQR58WcgdDtxkw4=; b=dDyX9JFawyxYd8RZ5Zh5pW6z32a0g3y/ci2VFsPVtv8aLklJ6pjA8oFU3rsTFsjUSb e1tJdFTjX/FtKnj4aGmcbptw8r1VPXEjZ23G8vRvEhP0Nr5y8Mn8jEKnSxypfsGZDS+N W1RybDFK+QbkfFf00CyXrfh0vBPeUR6V4hvBusQ7lcklkaYzrUN9t7WXQ4XTWcusQCaw moEQGX98gHE55DM0RxDfIzILt93nvGKmcwERy0/03FyLyKL5qxL+qm2RONjA3d41S67f Q+kXPSnR9yu9BkYBAGAKpNEOr4UtY5pcDGw5evAqqSaV68MYdaAZ2iey/Zxd8NvB5e9A a8jQ== X-Forwarded-Encrypted: i=1; AJvYcCXVAFpHS3QGeyOartJKC8sliS6mqGeiMtVC2kCfqyWK6D0orGj2U2pZIu80AQasz3eBkvYZV3c72wixuLQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yza/XKuo5oQzTmpUuyikp6tB+H6UnhmDoYroQUF1zMfyoTpD62R Hs+btWdpG6ovs4o/EJRqvfOLBhDKL6EiMOH2kmOWe43yI2DuUT1unxC/3ZdMc9tVHzf6InzyoO9 prjvzpiGFCsyVWiwBB9Dio1x3kc5wTJA9OgTpZMrEbDl8BSqlY8aHMVMZpG8IGV/MeAijhxdo8u I= X-Gm-Gg: AZuq6aKJBDL8rwsEN9FgRkUevdXrNv4Ru4zdogLxzJfdHCVAXV1G9V9/z6/pYpwQBXs rmt6u5ZgoJZhtBIJHcfAPNhPoAVU6yoWGXWVr5juNOM98EztIKK4ua5Xq7J3Pex0HRZwy9AoJ3V ejD6JojU5t6MmbzN/6qd9ns8yNQwfbT/tCkZeBdjXlR8mK7bdhkVkEwE01SaIXGYzin6+pSxZZ1 DK/EL0cWoy/SCyIWAviVqbtEOdZsdfh7QB8FXXbuKWsZI1taCio+vDqYi2PBz6JpkEf+o19SmBM NNClBSidJDmLnUl3e9wDh+xM9xOqYauAJm7frrnCA3bbwa4G14Ityhg1Ym1s1AzCSU0w99DqSya 8XhSa9esXFnnlUMtLq/YsbrI8q7RyX81JW94xJfmKezk7ww== X-Received: by 2002:a17:903:4b30:b0:2a9:5a0:22b5 with SMTP id d9443c01a7336-2a905a0235amr73670935ad.20.1770093098661; Mon, 02 Feb 2026 20:31:38 -0800 (PST) X-Received: by 2002:a17:903:4b30:b0:2a9:5a0:22b5 with SMTP id d9443c01a7336-2a905a0235amr73670565ad.20.1770093098071; Mon, 02 Feb 2026 20:31:38 -0800 (PST) Received: from hu-sushruts-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a88b4148d0sm162487605ad.27.2026.02.02.20.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 20:31:37 -0800 (PST) From: Sushrut Shree Trivedi Date: Tue, 03 Feb 2026 10:01:28 +0530 Subject: [PATCH v2 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260203-industrial-mezzanine-pcie-v2-1-8579ed6bf931@oss.qualcomm.com> References: <20260203-industrial-mezzanine-pcie-v2-0-8579ed6bf931@oss.qualcomm.com> In-Reply-To: <20260203-industrial-mezzanine-pcie-v2-0-8579ed6bf931@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sushrut Shree Trivedi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770093091; l=4391; i=sushrut.trivedi@oss.qualcomm.com; s=20251127; h=from:subject:message-id; bh=9mk67q2Nm7U9N4K8hxF/WDuU5gSRnJaaKjFBP7XeR7A=; b=Z7AixNHNBZoRfVT1fNMqaNXM6Qlkxj3ix1OmIYfuyf0g95/nU+6bh0i0t1FRCfr7CtpaKeOCW k63zcQV4tBoCXvNVVdTHN0w4sLMnM9FM/d9DzqQkMiwbA6rvScI2n0w X-Developer-Key: i=sushrut.trivedi@oss.qualcomm.com; a=ed25519; pk=OrUHTxBaSg1oY3CtCictJ5A4bDMNLRZS1S+QfD9pdjw= X-Authority-Analysis: v=2.4 cv=TaebdBQh c=1 sm=1 tr=0 ts=69817a2b cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=RBLAtJqH_bkH6XPhXP4A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: D6sPQGNJPl_tJwJ7VDYPTTQfp2cDbrrW X-Proofpoint-ORIG-GUID: D6sPQGNJPl_tJwJ7VDYPTTQfp2cDbrrW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDAzNCBTYWx0ZWRfX/YNHGvWqJ5DS tMksv8FdkiiKtOXmtVO2GMiz1wpYtHdzMZqU6jriHDICCCtZs1jKwUPBqO5/BfAOu5sN0M/urLj PzRwOqeHCbz8fi5rB0jj9lOPhMg6s+Ls2SX/sNG6xoA5QdVfFa/rm/Lw8QyAPlIwQ41p3SSMkdR qtPD4Ypy3EOUorSVHIlHjxMpVxj28jFLswiB5BsKmJsA22yhBq7/2wUjIcV0oySgOtYQ9LI8Phq d10WBYJ3DSdUEe46pQ4KzgWvEAI79F/0WCfNAIp/DSAPy3ZhcT35ubjdqt/YCBASD9IPikEwkqa Sgf6pZua8coUI3Q+L/7GlRvc6K6Xwvc+clHL9IwiedmA2iTRSJehZSWuddBjCMBY443+sNBLF8m 3xJDkELK30pIUROm7zv6d8IvXV+RvQ6FfGFKC9BTMTOZesmAHC33+79q//jC6uqApaycm69mD0c uP+aeQz66z1fom8Kz/g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_01,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030034 Add a node for the TC9563 PCIe switch connected to PCIe0. The switch has three downstream ports.Two embedded Ethernet devices are present on one of the downstream ports. All the ports present in the node represent the downstream ports and embedded endpoints. Power to the TC9563 is supplied through two LDO regulators, which are on by default and are added as fixed regulators. TC9563 can be configured through I2C. Signed-off-by: Sushrut Shree Trivedi --- .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 138 +++++++++++++++++= ++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.= dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 619a42b5ef48..89bbcab0908d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -5,9 +5,47 @@ =20 /dts-v1/; /plugin/; +#include #include #include =20 +&{/} { + + vreg_dc_12v: regulator-vreg-dc-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_DC_12V"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <24000000>; + regulator-max-microvolt =3D <24000000>; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + vin-supply =3D <&vreg_dc_12v>; + }; + + vreg_0p9: regulator-vreg-0p9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_0P9"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + vin-supply =3D <&vreg_dc_12v>; + }; +}; + &spi11 { #address-cells =3D <1>; #size-cells =3D <0>; @@ -19,3 +57,103 @@ st33htpm0: tpm@0 { spi-max-frequency =3D <20000000>; }; }; + +&pcie0 { + bus-range =3D <0x00 0xff>; + iommu-map =3D <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>, + <0x208 &apps_smmu 0x1c04 0x1>, + <0x210 &apps_smmu 0x1c05 0x1>, + <0x218 &apps_smmu 0x1c06 0x1>, + <0x300 &apps_smmu 0x1c07 0x1>, + <0x400 &apps_smmu 0x1c08 0x1>, + <0x500 &apps_smmu 0x1c09 0x1>, + <0x501 &apps_smmu 0x1c10 0x1>; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l10c_0p88>; + vdda-pll-supply =3D <&vreg_l6b_1p2>; + + status =3D "okay"; +}; + +&pcie0_port { + pcie0_switch0_usp: pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + + vddc-supply =3D <&vreg_0p9>; + vdd18-supply =3D <&vreg_1p8>; + vdd09-supply =3D <&vreg_0p9>; + vddio1-supply =3D <&vreg_1p8>; + vddio2-supply =3D <&vreg_1p8>; + vddio18-supply =3D <&vreg_1p8>; + + i2c-parent =3D <&i2c1 0x77>; + + resx-gpios =3D <&tlmm 78 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie0_tc9563_resx_n>; + pinctrl-names =3D "default"; + + pcie0_switch0_dsp1: pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + }; + + pcie0_switch0_dsp2: pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + }; + + pcie0_switch0_dsp3: pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + + pcie0_switch0_eth0: pci@0,0 { + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pcie0_switch0_eth1: pci@0,1 { + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + +&tlmm { + pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { + pins =3D "gpio78"; + function =3D "gpio"; + + bias-disable; + input-disable; + output-enable; + power-source =3D <0>; + }; +}; --=20 2.25.1 From nobody Mon Feb 9 19:43:04 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66D212264AD for ; Tue, 3 Feb 2026 04:31:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770093105; cv=none; b=dm50tIak205pnHuyPerig30oIYnloRxabKEzQACb26YTnd8GrZiJaCbpZYmQjBnALah61D4zReXglyCFvBwCEX+cOkuzCI6m51wYwVX86rxVHVSQNVlo/xpiTlg9wxR2cj+RKtNyifHX+Zk8wYa0Ywr698I+5DcYRGaLEpGDSkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770093105; c=relaxed/simple; bh=gfvMt7NZHc2g1A0esyJYlBNWDJF7SPNzJoPpYkTyNNQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q0JQnoLvdIWFAfLwLlXmAfKKdc8MGZiX7zAZKpZ1dyqiptbAITgcMqbzdrijLc2TYJo+pJT/nQRok3K8DjmR4D7hjmaJZq89HPWXpv9uDmjq+iT2+AbSnZdn09qdqVduyO8rJMNDaj/wGJBTxShXq0BltoPCUQcAyGF3mjSX5oE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Cn+IQrts; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ZyBozyqG; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Cn+IQrts"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ZyBozyqG" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 612L9qZv2884358 for ; Tue, 3 Feb 2026 04:31:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= lKu/JJZ4BgovY51L2puyItNkDkQw4dZ8GvhPS74zbi8=; b=Cn+IQrtsc3jYfuFJ vw64MyWo2CgkIABM+HRvqF3DdAuLiK6bib8QVoake8pMc6fXYbxY1bdhxER+cwAK fTpjgru1RVyB8exDzPw5WnBU3HXijtAGw2vShA5EWfNrpAUL5e/BJuzTo/UNmUQn c2YTVDhwwhYESMDj695142g74mFI/W/66aOFDUbc0sx/4iAJtfZFvUqau4y5T2Ay 0fmb8Snp0k16ooPCRMeBB9QzQqND9PmsduPzu90gCQIJNoLmD2rU0Yybtk7htwLA BXiza+5ybHDFIDPgPmsQzwk//EszFxXC620DBGL7kaG6qtc0KMCz8iTVEj/hJcl2 oDi5vg== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c2uu3jn6d-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 03 Feb 2026 04:31:42 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-352c79abf36so4631643a91.2 for ; Mon, 02 Feb 2026 20:31:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1770093102; x=1770697902; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lKu/JJZ4BgovY51L2puyItNkDkQw4dZ8GvhPS74zbi8=; b=ZyBozyqG5PPEg83KEBEB4Qako/MtIwRqTi5O2DjGZr59e0U0ZFpdgu/sg+eQSvvvRG W11iPlArSMBicdcQxN4uXnDGHktQnp3EZAU+b0/X/OEw/d4V7L2QATxRiPNmbdYmmbk/ 1+4r97ZP2b8lnhq1JGyHn+7MG61wN8Vjweu9EoGoCln2KHkDiqC3rdhOw4x0n4Cm24z9 NwFbxPfoANUDMqYHFms3e23MvV29xC1KnqZEYhBmQ95gWG3QfCC2kSCWQajU8uJOk2Ip n3BJNxSVk6baySSE/P7hLpDDHsbcR3NPuZVnA341I1CRD+gIR2DZov3Ox9FaFENIb25h WNWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770093102; x=1770697902; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=lKu/JJZ4BgovY51L2puyItNkDkQw4dZ8GvhPS74zbi8=; b=SdmsFN8s9kPDG62NMNVNchjCMFmqeakDi7m8vGYy+BVIfGeOnWnfCFc+YoNlU9ovPS pBt5stBwszsEaEFo+NOtsWDNvZydp5jN29NXd5XCmW/3sqC9Anv68N05hjSdVntbelj+ wrl5i8fTN8sljgAB5d+RyfCqcDu8ZfXtPiVa6Y6/rqEmQ16Y4ZInoRmvO9XMtuM41/et zTlpw8xXulaMlhvwOCRuk/i0OiTD+9fusou5zY2jvKJC7x+vAw6mui9hpyvmHfQkawtJ 7n/mlmqpwljRFehoF3VicuYkq0TZjeDlCeIT/HhI5CyemtiwQ1kp0g6mN9fIN9PPfQ40 JrXg== X-Forwarded-Encrypted: i=1; AJvYcCWjeWjKE4rl20FaIPLwp8IMvWqYdP46/MsgNgbp/m9vz3BxVEdgooSBs7pHyBKDOaMQSNzJPrUCO2fyWhc=@vger.kernel.org X-Gm-Message-State: AOJu0YxgoYwyaeN9sxB0uLU33ZtHNk+26pwbO6aLM/INkB7xjILNuEnR YzUWgSh758FGfAx5FPgGcpBiy53d3kDnhE6hg7+cxb12wm+lZqTvZk5UQ9W8JWVPYtIfQg5BKeM tMJO5PKkf3jXcxYJuVywvtwicZG1C9OViDPkoTLyWTgcKykEgZU6HmRne0ZCJOFSYi7w= X-Gm-Gg: AZuq6aKof4lNQIXvTcvnF4EmlZnSJ2sh+frB0OOjCICiQPyXgE17rvVHfVFH51uPgOM 1cyILqpYeDZJ4GdsSbuFo/TWM/wsmz1pXBIscCwcuBf/kK+BfIWW5zlMhNU9KJSUcKvBuyqEhUk J0WeR4wdSNCSDeM9V/EOvcp44e/Gw66gxFHsRkPeHGDBIdq8y2QoDquxOmVxrsREnGyvMxgjLyt xNV5yHMEWUutr9cKEkYaO5ppRrBbFNiBhUAJYylecANOrjQVjHZNgwC5XzkmlwNMUmh7mlQw795 RCxC+K26dEhOJssVcCqLqiMYNN6+ZrT8sHWpGvjg6+Apybh8k7RwupeGlYe32dHmu03ZsFBITE1 HOjxZ6d/ct3T4YRak7qQ6SIrVa2FhDALT8E70fnswTSSHlg== X-Received: by 2002:a17:903:38c8:b0:2a7:b039:4b52 with SMTP id d9443c01a7336-2a8d9591c81mr129069265ad.1.1770093101896; Mon, 02 Feb 2026 20:31:41 -0800 (PST) X-Received: by 2002:a17:903:38c8:b0:2a7:b039:4b52 with SMTP id d9443c01a7336-2a8d9591c81mr129069045ad.1.1770093101325; Mon, 02 Feb 2026 20:31:41 -0800 (PST) Received: from hu-sushruts-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a88b4148d0sm162487605ad.27.2026.02.02.20.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 20:31:41 -0800 (PST) From: Sushrut Shree Trivedi Date: Tue, 03 Feb 2026 10:01:29 +0530 Subject: [PATCH v2 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260203-industrial-mezzanine-pcie-v2-2-8579ed6bf931@oss.qualcomm.com> References: <20260203-industrial-mezzanine-pcie-v2-0-8579ed6bf931@oss.qualcomm.com> In-Reply-To: <20260203-industrial-mezzanine-pcie-v2-0-8579ed6bf931@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sushrut Shree Trivedi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770093091; l=5191; i=sushrut.trivedi@oss.qualcomm.com; s=20251127; h=from:subject:message-id; bh=gfvMt7NZHc2g1A0esyJYlBNWDJF7SPNzJoPpYkTyNNQ=; b=Dr15TWLJCayAvWplpQJZxyQrMULW2egbn58JknQ/kwzjU2niHFQR+TscCDNwh3K+3KQt7LmLF 916MneTeaQDCddPKkkTft8142WuBdXB+riw71JI3Pn/AC2XH0MJDs1T X-Developer-Key: i=sushrut.trivedi@oss.qualcomm.com; a=ed25519; pk=OrUHTxBaSg1oY3CtCictJ5A4bDMNLRZS1S+QfD9pdjw= X-Proofpoint-ORIG-GUID: 26I5fVUW0ys_doiUppI3nW_JDI8x8Ssq X-Authority-Analysis: v=2.4 cv=OrRCCi/t c=1 sm=1 tr=0 ts=69817a2e cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=RSE3UA2U0-qTjrSbjqYA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: 26I5fVUW0ys_doiUppI3nW_JDI8x8Ssq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDAzNCBTYWx0ZWRfX0BzK5ouaZhkK 7rYUDgl0JLUiyXXtC59fEwiRIIue/yj7QkX8hXrgl7DCzUwrCcnEa5a11v7owNeokHb7Uu5k9yP CMQfNZxupqIHaujYKP30bHHygjFTmtmBSOKLfVDks4TQeEYjHtVpLZdeH9jHqQLMA7OZWW5kXv9 MbE9d4tiWHNnvbkhtuVmYKH6Y3YsDtQ86yTCgOs20/5dC0LlgGOjNCTRu+Khy7+8jZI9t9xdtbN O9dpxD/niLcysG79sk879k7OuNy63e/s2xc3FCPzBwHQz8IJjws01xRxyW53hb/I94lLAzhAAKO eYvzUeVwIBzp+qnHjYICTc010Ta5JctRxq8+eZJE9cBoWHbaMaJlOjL2LncdDB64bDRjA6vMN3p 74WGdhOoRmuaJa5hZOrxt9DcuFYHZPLWxJryQUc9j8sHWa2JVjR+gcEYDUvhjhDYuVohT8kkyyt Db5ctr0eQqDZPPKke7A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_01,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 adultscore=0 malwarescore=0 phishscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030034 Add a node for the second TC9563 PCIe switch on PCIe1, which is connected in cascade to the first TC9563 switch via the former's downstream port. Two embedded Ethernet devices are present on one of the downstream ports of this second switch as well. All the ports present in the node represent the downstream ports and embedded endpoints. The second TC9563 is powered up via the same LDO regulators as the first one, and these can be controlled via two GPIOs, which are already present as fixed regulators. This TC9563 can also be configured through I2C. Signed-off-by: Sushrut Shree Trivedi --- .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 96 ++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +-- 2 files changed, 102 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.= dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 89bbcab0908d..1744c9c8bd50 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -146,6 +146,91 @@ pcie0_switch0_eth1: pci@0,1 { }; }; =20 +&pcie1 { + iommu-map =3D <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x408 &apps_smmu 0x1c90 0x1>, + <0x410 &apps_smmu 0x1c91 0x1>, + <0x418 &apps_smmu 0x1c92 0x1>, + <0x500 &apps_smmu 0x1c93 0x1>, + <0x600 &apps_smmu 0x1c94 0x1>, + <0x700 &apps_smmu 0x1c95 0x1>, + <0x701 &apps_smmu 0x1c96 0x1>, + <0x800 &apps_smmu 0x1c97 0x1>, + <0x900 &apps_smmu 0x1c98 0x1>, + <0x901 &apps_smmu 0x1c99 0x1>; +}; + +&pcie1_switch0_dsp1 { + pcie1_switch1_usp: pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x30000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + + vddc-supply =3D <&vdd_ntn_0p9>; + vdd18-supply =3D <&vdd_ntn_1p8>; + vdd09-supply =3D <&vdd_ntn_0p9>; + vddio1-supply =3D <&vdd_ntn_1p8>; + vddio2-supply =3D <&vdd_ntn_1p8>; + vddio18-supply =3D <&vdd_ntn_1p8>; + + i2c-parent =3D <&i2c1 0x33>; + + resx-gpios =3D <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie1_tc9563_resx_n>; + pinctrl-names =3D "default"; + + pcie1_switch1_dsp1: pcie@1,0 { + reg =3D <0x40800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + }; + + pcie1_switch1_dsp2: pcie@2,0 { + reg =3D <0x41000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + }; + + pcie1_switch1_dsp3: pcie@3,0 { + reg =3D <0x41800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + + pcie1_switch1_eth0: pci@0,0 { + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pcie1_switch1_eth1: pci@0,1 { + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + &tlmm { pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { pins =3D "gpio78"; @@ -156,4 +241,15 @@ pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { output-enable; power-source =3D <0>; }; + + pcie1_tc9563_resx_n: pcie1-tc9563-resx-state { + pins =3D "gpio124"; + function =3D "gpio"; + + bias-disable; + input-disable; + output-enable; + power-source =3D <0>; + }; + }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot= /dts/qcom/qcs6490-rb3gen2.dts index e3d2f01881ae..ffe4521eb289 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -828,7 +828,7 @@ &pcie1_phy { }; =20 &pcie1_port0 { - pcie@0,0 { + pcie1_switch0_usp: pcie@0,0 { compatible =3D "pci1179,0623"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; #address-cells =3D <3>; @@ -852,7 +852,7 @@ pcie@0,0 { pinctrl-0 =3D <&tc9563_resx_n>; pinctrl-names =3D "default"; =20 - pcie@1,0 { + pcie1_switch0_dsp1: pcie@1,0 { reg =3D <0x20800 0x0 0x0 0x0 0x0>; #address-cells =3D <3>; #size-cells =3D <2>; @@ -862,7 +862,7 @@ pcie@1,0 { bus-range =3D <0x3 0xff>; }; =20 - pcie@2,0 { + pcie1_switch0_dsp2: pcie@2,0 { reg =3D <0x21000 0x0 0x0 0x0 0x0>; #address-cells =3D <3>; #size-cells =3D <2>; @@ -872,7 +872,7 @@ pcie@2,0 { bus-range =3D <0x4 0xff>; }; =20 - pcie@3,0 { + pcie1_switch0_dsp3: pcie@3,0 { reg =3D <0x21800 0x0 0x0 0x0 0x0>; #address-cells =3D <3>; #size-cells =3D <2>; @@ -880,7 +880,7 @@ pcie@3,0 { ranges; bus-range =3D <0x5 0xff>; =20 - pci@0,0 { + pcie1_switch0_eth0: pci@0,0 { reg =3D <0x50000 0x0 0x0 0x0 0x0>; #address-cells =3D <3>; #size-cells =3D <2>; @@ -888,7 +888,7 @@ pci@0,0 { ranges; }; =20 - pci@0,1 { + pcie1_switch0_eth1: pci@0,1 { reg =3D <0x50100 0x0 0x0 0x0 0x0>; #address-cells =3D <3>; #size-cells =3D <2>; --=20 2.25.1