Aggre1-noc interconnect node on QCS615 has QoS registers located
inside a block whose interface is clock-gated. For that node,
driver must enable the corresponding clock(s) before accessing
the registers. Add the 'clocks' property so the driver can obtain
and enable the required clock(s).
Only interconnects that have clock‑gated QoS register interface
use this property; it is not applicable to all interconnect nodes.
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
---
.../interconnect/qcom,qcs615-rpmh.yaml | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
index e06404828824..096a9064cc01 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
@@ -34,6 +34,10 @@ properties:
reg:
maxItems: 1
+ clocks:
+ minItems: 3
+ maxItems: 3
+
required:
- compatible
@@ -53,6 +57,36 @@ allOf:
required:
- reg
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs615-aggre1-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS PHY AXI clock
+ - description: aggre USB2 SEC AXI clock
+ - description: aggre USB3 PRIM AXI clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs615-camnoc-virt
+ - qcom,qcs615-config-noc
+ - qcom,qcs615-dc-noc
+ - qcom,qcs615-gem-noc
+ - qcom,qcs615-mc-virt
+ - qcom,qcs615-mmss-noc
+ - qcom,qcs615-system-noc
+ then:
+ properties:
+ clocks: false
+
unevaluatedProperties: false
examples:
@@ -69,3 +103,13 @@ examples:
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
+
+ aggre1_noc: interconnect@1700000 {
+ compatible = "qcom,qcs615-aggre1-noc";
+ reg = <0x1700000 0x3f200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc_aggre_ufs_phy_axi_clk>,
+ <&gcc_aggre_usb2_sec_axi_clk>,
+ <&gcc_aggre_usb3_prim_axi_clk>;
+ };
--
2.43.0
On 2/2/26 8:05 AM, Odelu Kukatla wrote: > Aggre1-noc interconnect node on QCS615 has QoS registers located > inside a block whose interface is clock-gated. For that node, > driver must enable the corresponding clock(s) before accessing > the registers. Add the 'clocks' property so the driver can obtain > and enable the required clock(s). > > Only interconnects that have clock‑gated QoS register interface > use this property; it is not applicable to all interconnect nodes. > > Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> > --- > .../interconnect/qcom,qcs615-rpmh.yaml | 44 +++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml > index e06404828824..096a9064cc01 100644 > --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml > +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml > @@ -34,6 +34,10 @@ properties: > reg: > maxItems: 1 > > + clocks: > + minItems: 3 > + maxItems: 3 > + > required: > - compatible > > @@ -53,6 +57,36 @@ allOf: > required: > - reg > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,qcs615-aggre1-noc > + then: > + properties: > + clocks: > + items: > + - description: aggre UFS PHY AXI clock > + - description: aggre USB2 SEC AXI clock > + - description: aggre USB3 PRIM AXI clock Should we also include the IPA clock here? Konrad
On 2/2/2026 4:33 PM, Konrad Dybcio wrote: > On 2/2/26 8:05 AM, Odelu Kukatla wrote: >> Aggre1-noc interconnect node on QCS615 has QoS registers located >> inside a block whose interface is clock-gated. For that node, >> driver must enable the corresponding clock(s) before accessing >> the registers. Add the 'clocks' property so the driver can obtain >> and enable the required clock(s). >> >> Only interconnects that have clock‑gated QoS register interface >> use this property; it is not applicable to all interconnect nodes. >> >> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> >> --- >> .../interconnect/qcom,qcs615-rpmh.yaml | 44 +++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml >> index e06404828824..096a9064cc01 100644 >> --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml >> +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml >> @@ -34,6 +34,10 @@ properties: >> reg: >> maxItems: 1 >> >> + clocks: >> + minItems: 3 >> + maxItems: 3 >> + >> required: >> - compatible >> >> @@ -53,6 +57,36 @@ allOf: >> required: >> - reg >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,qcs615-aggre1-noc >> + then: >> + properties: >> + clocks: >> + items: >> + - description: aggre UFS PHY AXI clock >> + - description: aggre USB2 SEC AXI clock >> + - description: aggre USB3 PRIM AXI clock > > Should we also include the IPA clock here? > Thanks for the review! For QCS615, the IPA clock is already enabled by the bootloader (xBL) and kept on during the boot‑up stage. Because of this, we do not need to explicitly enable the IPA clock in the interconnect driver when accessing the QoS registers. Thanks, Odelu > Konrad
On 2/5/26 7:06 AM, Odelu Kukatla wrote: > > > On 2/2/2026 4:33 PM, Konrad Dybcio wrote: >> On 2/2/26 8:05 AM, Odelu Kukatla wrote: >>> Aggre1-noc interconnect node on QCS615 has QoS registers located >>> inside a block whose interface is clock-gated. For that node, >>> driver must enable the corresponding clock(s) before accessing >>> the registers. Add the 'clocks' property so the driver can obtain >>> and enable the required clock(s). >>> >>> Only interconnects that have clock‑gated QoS register interface >>> use this property; it is not applicable to all interconnect nodes. >>> >>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> >>> --- [...] >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - qcom,qcs615-aggre1-noc >>> + then: >>> + properties: >>> + clocks: >>> + items: >>> + - description: aggre UFS PHY AXI clock >>> + - description: aggre USB2 SEC AXI clock >>> + - description: aggre USB3 PRIM AXI clock >> >> Should we also include the IPA clock here? >> > > Thanks for the review! > > For QCS615, the IPA clock is already enabled by the bootloader (xBL) and > kept on during the boot‑up stage. Because of this, we do not need to > explicitly enable the IPA clock in the interconnect driver when > accessing the QoS registers. Would we need to re-enable it to re-program the hardware if say the icc module is loaded after unused clk cleanup or after a cx collapse? Konrad
On 2/5/2026 2:31 PM, Konrad Dybcio wrote: > On 2/5/26 7:06 AM, Odelu Kukatla wrote: >> >> >> On 2/2/2026 4:33 PM, Konrad Dybcio wrote: >>> On 2/2/26 8:05 AM, Odelu Kukatla wrote: >>>> Aggre1-noc interconnect node on QCS615 has QoS registers located >>>> inside a block whose interface is clock-gated. For that node, >>>> driver must enable the corresponding clock(s) before accessing >>>> the registers. Add the 'clocks' property so the driver can obtain >>>> and enable the required clock(s). >>>> >>>> Only interconnects that have clock‑gated QoS register interface >>>> use this property; it is not applicable to all interconnect nodes. >>>> >>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> >>>> --- > > [...] > >>>> + - if: >>>> + properties: >>>> + compatible: >>>> + contains: >>>> + enum: >>>> + - qcom,qcs615-aggre1-noc >>>> + then: >>>> + properties: >>>> + clocks: >>>> + items: >>>> + - description: aggre UFS PHY AXI clock >>>> + - description: aggre USB2 SEC AXI clock >>>> + - description: aggre USB3 PRIM AXI clock >>> >>> Should we also include the IPA clock here? >>> >> >> Thanks for the review! >> >> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and >> kept on during the boot‑up stage. Because of this, we do not need to >> explicitly enable the IPA clock in the interconnect driver when >> accessing the QoS registers. > > Would we need to re-enable it to re-program the hardware if say the > icc module is loaded after unused clk cleanup or after a cx collapse? > IPA clock is not managed by GCC clock controller driver, so clk_disable_unused does not disable it. As a result, the icc provider does not need to re enable an IPA clock for QoS access after unused clk cleanup. And QCS615 does *not* support Cx collapse. Thanks, Odelu > Konrad
On Thu, Feb 05, 2026 at 03:10:31PM +0530, Odelu Kukatla wrote: > > > On 2/5/2026 2:31 PM, Konrad Dybcio wrote: > > On 2/5/26 7:06 AM, Odelu Kukatla wrote: > >> > >> > >> On 2/2/2026 4:33 PM, Konrad Dybcio wrote: > >>> On 2/2/26 8:05 AM, Odelu Kukatla wrote: > >>>> Aggre1-noc interconnect node on QCS615 has QoS registers located > >>>> inside a block whose interface is clock-gated. For that node, > >>>> driver must enable the corresponding clock(s) before accessing > >>>> the registers. Add the 'clocks' property so the driver can obtain > >>>> and enable the required clock(s). > >>>> > >>>> Only interconnects that have clock‑gated QoS register interface > >>>> use this property; it is not applicable to all interconnect nodes. > >>>> > >>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> > >>>> --- > > > > [...] > > > >>>> + - if: > >>>> + properties: > >>>> + compatible: > >>>> + contains: > >>>> + enum: > >>>> + - qcom,qcs615-aggre1-noc > >>>> + then: > >>>> + properties: > >>>> + clocks: > >>>> + items: > >>>> + - description: aggre UFS PHY AXI clock > >>>> + - description: aggre USB2 SEC AXI clock > >>>> + - description: aggre USB3 PRIM AXI clock > >>> > >>> Should we also include the IPA clock here? > >>> > >> > >> Thanks for the review! > >> > >> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and > >> kept on during the boot‑up stage. Because of this, we do not need to > >> explicitly enable the IPA clock in the interconnect driver when > >> accessing the QoS registers. > > > > Would we need to re-enable it to re-program the hardware if say the > > icc module is loaded after unused clk cleanup or after a cx collapse? > > > > IPA clock is not managed by GCC clock controller driver, so > clk_disable_unused does not disable it. The clk_disable_unused is not limited to the GCC. The clock is managed by the clk-rpmh, so clk_disable_unused applies to it too. > As a result, the icc provider > does not need to re enable an IPA clock for QoS access after unused clk > cleanup. And QCS615 does *not* support Cx collapse. Does lack of CX collapse apply to SM6150? -- With best wishes Dmitry
On 2/5/2026 3:59 PM, Dmitry Baryshkov wrote: > On Thu, Feb 05, 2026 at 03:10:31PM +0530, Odelu Kukatla wrote: >> >> >> On 2/5/2026 2:31 PM, Konrad Dybcio wrote: >>> On 2/5/26 7:06 AM, Odelu Kukatla wrote: >>>> >>>> >>>> On 2/2/2026 4:33 PM, Konrad Dybcio wrote: >>>>> On 2/2/26 8:05 AM, Odelu Kukatla wrote: >>>>>> Aggre1-noc interconnect node on QCS615 has QoS registers located >>>>>> inside a block whose interface is clock-gated. For that node, >>>>>> driver must enable the corresponding clock(s) before accessing >>>>>> the registers. Add the 'clocks' property so the driver can obtain >>>>>> and enable the required clock(s). >>>>>> >>>>>> Only interconnects that have clock‑gated QoS register interface >>>>>> use this property; it is not applicable to all interconnect nodes. >>>>>> >>>>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> >>>>>> --- >>> >>> [...] >>> >>>>>> + - if: >>>>>> + properties: >>>>>> + compatible: >>>>>> + contains: >>>>>> + enum: >>>>>> + - qcom,qcs615-aggre1-noc >>>>>> + then: >>>>>> + properties: >>>>>> + clocks: >>>>>> + items: >>>>>> + - description: aggre UFS PHY AXI clock >>>>>> + - description: aggre USB2 SEC AXI clock >>>>>> + - description: aggre USB3 PRIM AXI clock >>>>> >>>>> Should we also include the IPA clock here? >>>>> >>>> >>>> Thanks for the review! >>>> >>>> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and >>>> kept on during the boot‑up stage. Because of this, we do not need to >>>> explicitly enable the IPA clock in the interconnect driver when >>>> accessing the QoS registers. >>> >>> Would we need to re-enable it to re-program the hardware if say the >>> icc module is loaded after unused clk cleanup or after a cx collapse? >>> >> >> IPA clock is not managed by GCC clock controller driver, so >> clk_disable_unused does not disable it. > > The clk_disable_unused is not limited to the GCC. The clock is managed > by the clk-rpmh, so clk_disable_unused applies to it too. > clk_disable_unused()/clk_disable_unused_subtree() does not disable RPMh managed clocks, so it does not apply to IPA clock. >> As a result, the icc provider >> does not need to re enable an IPA clock for QoS access after unused clk >> cleanup. And QCS615 does *not* support Cx collapse. > > Does lack of CX collapse apply to SM6150? > SM6150, QCS615, and Talos are all names referring to the same underlying SoC family. Thanks, Odelu
On Fri, Feb 06, 2026 at 10:28:15AM +0530, Odelu Kukatla wrote: > > > On 2/5/2026 3:59 PM, Dmitry Baryshkov wrote: > > On Thu, Feb 05, 2026 at 03:10:31PM +0530, Odelu Kukatla wrote: > >> > >> > >> On 2/5/2026 2:31 PM, Konrad Dybcio wrote: > >>> On 2/5/26 7:06 AM, Odelu Kukatla wrote: > >>>> > >>>> > >>>> On 2/2/2026 4:33 PM, Konrad Dybcio wrote: > >>>>> On 2/2/26 8:05 AM, Odelu Kukatla wrote: > >>>>>> Aggre1-noc interconnect node on QCS615 has QoS registers located > >>>>>> inside a block whose interface is clock-gated. For that node, > >>>>>> driver must enable the corresponding clock(s) before accessing > >>>>>> the registers. Add the 'clocks' property so the driver can obtain > >>>>>> and enable the required clock(s). > >>>>>> > >>>>>> Only interconnects that have clock‑gated QoS register interface > >>>>>> use this property; it is not applicable to all interconnect nodes. > >>>>>> > >>>>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> > >>>>>> --- > >>> > >>> [...] > >>> > >>>>>> + - if: > >>>>>> + properties: > >>>>>> + compatible: > >>>>>> + contains: > >>>>>> + enum: > >>>>>> + - qcom,qcs615-aggre1-noc > >>>>>> + then: > >>>>>> + properties: > >>>>>> + clocks: > >>>>>> + items: > >>>>>> + - description: aggre UFS PHY AXI clock > >>>>>> + - description: aggre USB2 SEC AXI clock > >>>>>> + - description: aggre USB3 PRIM AXI clock > >>>>> > >>>>> Should we also include the IPA clock here? > >>>>> > >>>> > >>>> Thanks for the review! > >>>> > >>>> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and > >>>> kept on during the boot‑up stage. Because of this, we do not need to > >>>> explicitly enable the IPA clock in the interconnect driver when > >>>> accessing the QoS registers. > >>> > >>> Would we need to re-enable it to re-program the hardware if say the > >>> icc module is loaded after unused clk cleanup or after a cx collapse? > >>> > >> > >> IPA clock is not managed by GCC clock controller driver, so > >> clk_disable_unused does not disable it. > > > > The clk_disable_unused is not limited to the GCC. The clock is managed > > by the clk-rpmh, so clk_disable_unused applies to it too. > > > > clk_disable_unused()/clk_disable_unused_subtree() does not disable RPMh > managed clocks, so it does not apply to IPA clock. You are describing the current behaviour of one OS. The DTS should be describing the hardware. Other platforms describe IPA clock used by the aggre NoC nodes. > > >> As a result, the icc provider > >> does not need to re enable an IPA clock for QoS access after unused clk > >> cleanup. And QCS615 does *not* support Cx collapse. > > > > Does lack of CX collapse apply to SM6150? > > > > SM6150, QCS615, and Talos are all names referring to the same underlying > SoC family. Ack, I was making sure that lack of CX collapse isn't related to IoT vs mobile case. -- With best wishes Dmitry
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