Add support for LS7A LPC IRQ for MIPS Loongson systems

[PATCH 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

Posted by Icenowy Zheng 1 week, 1 day ago

This patchset tries to add support for Loongson 7A1000 PCH's LPC IRQ
controller to MIPS-based Loongson systems.

LPC, from software's perspective of view, is just ISA, so the IRQs
should be handled as legacy ones occupying the lowest 0-15 IRQ numbers.
Despite the current PCH LPC driver for ACPI-based LoongArch Loongson
machines handled it, the setup is fragile and depends on its specific
setup sequence (allocating the LPC IRQs first, and then allocate the
parent IRQ at PCH PIC). The refactor of extracting parent IRQ allocation
breaks this fragile sequence, so the first commit is created to address
for this issue (by reserving ISA IRQs from the dynamic IRQ allocation
space).

Then the remaining commits are just adding OF(DT) based initialization
of PCH LPC IRQ controller, like what happened on PCH PIC.

Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse as
integrated ones. I don't own a LoongArch-based device with LPC
peripherals, so test on LoongArch machines are welcomed.

Icenowy Zheng (8):
  genirq: reserve NR_IRQS_LEGACY IRQs by default
  dt-bindings: interrupt-controller: add LS7A PCH LPC
  irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init
  irqchip/loongson-pch-lpc: guard ACPI init code with CONFIG_ACPI
  irqchip/loongson-pch-lpc: add OF init code
  irqchip/loongson-pch-lpc: enable building on MIPS Loongson64
  MIPS: Loongson64: dts: sort nodes
  MIPS: Loongson64: dts: add node for LS7A PCH LPC

 .../loongson,pch-lpc.yaml                     | 52 +++++++++++
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi     | 17 +++-
 drivers/irqchip/Kconfig                       |  1 -
 drivers/irqchip/irq-loongson-pch-lpc.c        | 86 ++++++++++++++-----
 kernel/softirq.c                              |  2 +-
 5 files changed, 132 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml

-- 
2.52.0

Re: [PATCH 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems

Posted by Yao Zi 1 week ago

On Sat, Jan 31, 2026 at 05:45:39PM +0800, Icenowy Zheng wrote:
> This patchset tries to add support for Loongson 7A1000 PCH's LPC IRQ
> controller to MIPS-based Loongson systems.
> 
> LPC, from software's perspective of view, is just ISA, so the IRQs
> should be handled as legacy ones occupying the lowest 0-15 IRQ numbers.
> Despite the current PCH LPC driver for ACPI-based LoongArch Loongson
> machines handled it, the setup is fragile and depends on its specific
> setup sequence (allocating the LPC IRQs first, and then allocate the
> parent IRQ at PCH PIC). The refactor of extracting parent IRQ allocation
> breaks this fragile sequence, so the first commit is created to address
> for this issue (by reserving ISA IRQs from the dynamic IRQ allocation
> space).
> 
> Then the remaining commits are just adding OF(DT) based initialization
> of PCH LPC IRQ controller, like what happened on PCH PIC.
> 
> Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse as
> integrated ones. I don't own a LoongArch-based device with LPC
> peripherals, so test on LoongArch machines are welcomed.

Tested on TongFang L860-T2 system, which is LoongArch-based and exposes
keyboard and mouse as i8042, too. Nothing breaks with this series,

$ cat /proc/interrupts
           CPU0       CPU1       CPU2       CPU3
  1:        606          0          0          0  PCH LPC   1  i8042
 12:        645          0          0          0  PCH LPC  12  i8042
 20:      16393      14853      15443      17386  CPUINTC  12  IPI
 21:       4515       4154       3756       3701  CPUINTC  11  timer
 22:          0          0          0          0  PCH PIC   1  acpi
 28:          0          0          0          0  PCH PIC   7  loongson-alarm
 29:          0          0          0          0  PCH PIC   8  ls2x-i2c, ls2x-i2c, ls2x-i2c, ls2x-i2c, ls2x-i2c, ls2x-i2c
 37:          0          0          0          0 PCH-PCI-MSI-0000:00:09.0   0  PCIe bwctrl
 39:          0          0          0          0 PCH-PCI-MSI-0000:00:0a.0   0  PCIe bwctrl
 41:          0          0          0          0 PCH-PCI-MSI-0000:00:0b.0   0  PCIe bwctrl
 43:          0          0          0          0 PCH-PCI-MSI-0000:00:0c.0   0  PCIe bwctrl
 45:          0          0          0          0 PCH-PCI-MSI-0000:00:0d.0   0  PCIe bwctrl
 47:          0          0          0          0 PCH-PCI-MSI-0000:00:11.0   0  PCIe bwctrl
 49:          0          0          0          0 PCH-PCI-MSI-0000:00:13.0   0  PCIe bwctrl
 50:          0          0          0          0  PCH PIC  21  ahci[0000:00:08.0]
 51:         14          0          0          0 PCH-PCI-MSIX-0000:06:00.0   0  nvme0q0
 52:          0          0          0          0  PCH PIC  22  ahci[0000:00:08.1]
 53:          0          0          0          0  PCH PIC  23  ahci[0000:00:08.2]
 54:          0          0          0          0 PCH-PCI-MSI-0000:04:00.0   0  ahci[0000:04:00.0]
 55:        952          0          0          0 PCH-PCI-MSIX-0000:06:00.0   1  nvme0q1
 56:          0       1590          0          0 PCH-PCI-MSIX-0000:06:00.0   2  nvme0q2
 57:          0          0        916          0 PCH-PCI-MSIX-0000:06:00.0   3  nvme0q3
 58:          0          0          0       3836 PCH-PCI-MSIX-0000:06:00.0   4  nvme0q4
 61:       2649          0          0          0 PCH-PCI-MSI-0000:07:00.0   0  amdgpu
 62:       2561          0          0          0 PCH-PCI-MSI-0000:01:00.0   0  iwlwifi
IPI0:        350        507        573        311 LoongArch  1  Rescheduling interrupts
IPI1:      16044      14345      14870      17074 LoongArch  2  Function call interrupts
IPI2:          0          0          0          0 LoongArch  3  IRQ work interrupts
IPI3:          0          0          0          0 LoongArch  4  Clear vector interrupts
ERR:         12

Tested-by: Yao Zi <me@ziyao.cc>

Thanks for your work!

Regards,
Yao Zi