From nobody Mon Feb 9 08:59:47 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CBC6275AEB; Sat, 31 Jan 2026 09:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852771; cv=none; b=M9FAEtyGF3AlXy56txrvXGiXtujdNOAQuNyCMmYnexBNNQ1CcxXIKftDOEIG+qrZsgVPHJhf7t8fJAIQwFkoPzq4cL4xZME6MXCC1mboob7TnilNfCpcQYu0TQOvLcbFSx8j4QblZSphx+2gIiQAGhlbni+zZDLG+Wzy6jbKjGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852771; c=relaxed/simple; bh=F/HOxzCJ+d6erv3pLy8YREVLhjqD+8zeMOqYr1zgLDs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cWlR5U/GSBIAsecvfqeqth2mtWj5SZxeOszvkP8rVN6qEHSQTSpDmEboxpgQag6bWDDrXUQKq/lmGIbuNm+8TxVGFyZbYpYYi8c4nwbQsD8lab/7/OKYY5zeiyfdt+3Eq77GLHvzoIWIg2gN027lODw7zUotjnH+6cz+ccYYlBI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.102.235]) by APP-05 (Coremail) with SMTP id zQCowAC3Sw9Rz31p9UgiBw--.57463S3; Sat, 31 Jan 2026 17:46:01 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Huacai Chen , Jiaxun Yang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Icenowy Zheng , linux-s390@vger.kernel.org, Heiko Carstens , Vasily Gorbik , Alexander Gordeev Subject: [PATCH 1/8] genirq: reserve NR_IRQS_LEGACY IRQs in dynirq by default Date: Sat, 31 Jan 2026 17:45:40 +0800 Message-ID: <20260131094547.455916-2-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> References: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAC3Sw9Rz31p9UgiBw--.57463S3 X-Coremail-Antispam: 1UD129KBjvJXoW7urWkXFW5Zw17XFWDAr1xGrg_yoW8ZF48pr WxWry3W34xJ347Za45Ww1S9a4fua95G342kF9Ikw13Zwn8JrnYv3sa9F45Xr10vrs5GF4Y yFya9Fy5Xa4DZFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPE14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1le2I2 62IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcV AFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG 0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI 1lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_ Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17 CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0 I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I 8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73 UjIFyTuYvjfU8XdbUUUUU X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Several architectures define NR_IRQS_LEGACY to reserve a low range of IRQ numbers for fixed legacy allocations (e.g. ISA interrupts) which should not be handed out by the dynamic IRQ allocator. arch_dynirq_lower_bound() exists to enforce this, but today only x86 wires it up. In the current boot order this typically works because legacy IRQ domains register early and claim the low IRQ numbers first; however, that assumption breaks if the legacy controller is probed later. Make the default arch_dynirq_lower_bound() implementation honour NR_IRQS_LEGACY by clamping the allocation start to at least that value. Architectures that do not define NR_IRQS_LEGACY keep the current behaviour (effectively 0). Arm/PowerPC/MIPS/LoongArch use legacy IRQ domains for ISA interrupts and benefit from this change. x86 and s390 already provide their own implementations. Cc: linux-s390@vger.kernel.org Cc: Heiko Carstens Cc: Vasily Gorbik Cc: Alexander Gordeev Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Icenowy Zheng Tested-by: Yao Zi --- If this change turns out to be problematic for any architecture, we can always override arch_dynirq_lower_bound() for MIPS and LoongArch only. BTW it looks that S390 has a arch_dynirq_lower_bound() override that has the same behavior, but not with the same code. This is why S390 maintainers are Cc'ed by this patch. kernel/softirq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/softirq.c b/kernel/softirq.c index 77198911b8dd4..cdc77d52c36b2 100644 --- a/kernel/softirq.c +++ b/kernel/softirq.c @@ -1184,5 +1184,5 @@ int __init __weak arch_early_irq_init(void) =20 unsigned int __weak arch_dynirq_lower_bound(unsigned int from) { - return from; + return MAX(from, NR_IRQS_LEGACY); } --=20 2.52.0 From nobody Mon Feb 9 08:59:47 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81E6D2D2496; Sat, 31 Jan 2026 09:46:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852772; cv=none; b=R/2JaUu/JAjj09ZnaHnBGc1+oUV4zEzcyDrEJAqCPDr4si6DeOrQhn7GXW5482BSTkBHWxH1do3hAjQ3bMSrgPZL1zEmJ8Dv1Tj3MH+YzfthtKS3BTaeihbm7hQaF1pkpUMIwkkrJ44s79VrKQtC5EolT6m2Arwrpgxk5Ygme+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852772; c=relaxed/simple; bh=shMbLGZHM/sh1xXyGXCdDY0fKKks/y6FdTRXE2Z2aPI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IHUYKwmpdDvZ86jtx1ZUfZqRRI5vrQNsKkD7wkSGCQ76dxllk2tBkCrLLtEep1Hl25kDa8Nr7xkFWaJssTVXv0tTP5UbsRR9BT9ri+5bNe5mB+yWjkPrjzsudiPZzQm64LP+s3Ct9Na6cRkCqA6l2DmaukSD6YBRBHaFV7Y5+GM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.102.235]) by APP-05 (Coremail) with SMTP id zQCowAC3Sw9Rz31p9UgiBw--.57463S4; Sat, 31 Jan 2026 17:46:02 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Huacai Chen , Jiaxun Yang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Icenowy Zheng Subject: [PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC Date: Sat, 31 Jan 2026 17:45:41 +0800 Message-ID: <20260131094547.455916-3-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> References: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAC3Sw9Rz31p9UgiBw--.57463S4 X-Coremail-Antispam: 1UD129KBjvJXoW7tr15XrW7Ar47Wr17Kw4rXwb_yoW8ZFykpF 45C3ZxWr48tF13C3yFga40kF13Zr98ArnxCws7tw47Gr9Fga4UX3yakF95X3WfGr9rXa47 ZFyF93W8KwnrJF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7 AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE 2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcV C2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2Kfnx nUUI43ZEXa7VUbH5lUUUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Loongson 7A series PCH contains an LPC controller with an interrupt controller. Add the device tree binding for the interrupt controller. Signed-off-by: Icenowy Zheng Tested-by: Yao Zi --- .../loongson,pch-lpc.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= loongson,pch-lpc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongso= n,pch-lpc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loo= ngson,pch-lpc.yaml new file mode 100644 index 0000000000000..c00fbf31f47f0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-l= pc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson PCH LPC Controller + +maintainers: + - Jiaxun Yang + +description: + This interrupt controller is found in the Loongson LS7A family of PCH for + accepting interrupts sent by LPC-connected peripherals and signalling PIC + via a single interrupt line when interrupts are available. + +properties: + compatible: + const: loongson,pch-lpc-1.0 + + reg: + maxItems: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - interrupt-controller + - interrupts + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + #include + lpc: interrupt-controller@10002000 { + compatible =3D "loongson,pch-lpc-1.0"; + reg =3D <0x10002000 0x400>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&pic>; + interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; + }; +... --=20 2.52.0 From nobody Mon Feb 9 08:59:47 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81EEB2D7DF6; Sat, 31 Jan 2026 09:46:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852772; cv=none; b=l+x9Cdoc0z5p8jPbaVslm+eYlMjBAioi47JSsBSuFMw3t3PjORMiRllVQVJYHyPN5qzMjBsU50vLv1qMpX5Ucvp85ukMEvyjrRXyPmp9WMIJcPOrFROAk2i+7iYkzIWmdnKWfVG/obLbSy/atI73Fg2awwCuttlbDaw6qeELXEQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852772; c=relaxed/simple; bh=2/0SQmnmvBqbY6TnokaNX+wGYsWhkut5dqzPNDpjqAE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qACihEOZubsTScaamXyGqxy0L5Vv6BtUN/Wx64Da7tWPubc4dzpd4UBKXsMYPHS8wvbA/ahrfUzxNXmu2W11PIIKXff3llnAweEwMI8qSiqyXMOW3YaJcfg67h9r8ZHzteYIpCE7S1J1nW/nFHKr7RW8k4ZFA2EHIax5HrA7zHA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.102.235]) by APP-05 (Coremail) with SMTP id zQCowAC3Sw9Rz31p9UgiBw--.57463S5; Sat, 31 Jan 2026 17:46:06 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Huacai Chen , Jiaxun Yang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Icenowy Zheng Subject: [PATCH 3/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init Date: Sat, 31 Jan 2026 17:45:42 +0800 Message-ID: <20260131094547.455916-4-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> References: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAC3Sw9Rz31p9UgiBw--.57463S5 X-Coremail-Antispam: 1UD129KBjvJXoWxJw17Cw17JrW7Cr17uFyUWrg_yoWrXr4fpF W5Xa4avF45JF40gr1kC3WDZ3y3Cw1SkayUAFWfC34fJrnF9r1vkF10y3ZrZF4fArW5WF45 Zr4qv3W8CFnxAaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7 AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE 2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcV C2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2Kfnx nUUI43ZEXa7VUbpwZ7UUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" A lot of code could be shared between the current ACPI init flow with the possible OF init flow. Extract them to a dedicated function. The re-ordering of parent IRQ acquisition requires the arch code to reserve legacy IRQs from dynirq allocation via overriding arch_dynirq_lower_bound(), otherwise the parent of LPC irqchip will be allocated to the intended static range of LPC IRQs, which leads to allocation failure of LPC IRQs. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Icenowy Zheng Tested-by: Yao Zi --- drivers/irqchip/irq-loongson-pch-lpc.c | 56 +++++++++++++++++--------- 1 file changed, 36 insertions(+), 20 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-l= oongson-pch-lpc.c index 3a125f3e42873..4507000b991a6 100644 --- a/drivers/irqchip/irq-loongson-pch-lpc.c +++ b/drivers/irqchip/irq-loongson-pch-lpc.c @@ -175,13 +175,11 @@ static struct syscore pch_lpc_syscore =3D { .ops =3D &pch_lpc_syscore_ops, }; =20 -int __init pch_lpc_acpi_init(struct irq_domain *parent, - struct acpi_madt_lpc_pic *acpi_pchlpc) +static int __init pch_lpc_init(phys_addr_t addr, unsigned long size, + struct fwnode_handle *irq_handle, + int parent_irq) { - int parent_irq; struct pch_lpc *priv; - struct irq_fwspec fwspec; - struct fwnode_handle *irq_handle; =20 priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -189,7 +187,7 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, =20 raw_spin_lock_init(&priv->lpc_lock); =20 - priv->base =3D ioremap(acpi_pchlpc->address, acpi_pchlpc->size); + priv->base =3D ioremap(addr, size); if (!priv->base) goto free_priv; =20 @@ -198,12 +196,6 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, goto iounmap_base; } =20 - irq_handle =3D irq_domain_alloc_named_fwnode("lpcintc"); - if (!irq_handle) { - pr_err("Unable to allocate domain handle\n"); - goto iounmap_base; - } - /* * The LPC interrupt controller is a legacy i8259-compatible device, * which requires a static 1:1 mapping for IRQs 0-15. @@ -213,15 +205,10 @@ int __init pch_lpc_acpi_init(struct irq_domain *paren= t, &pch_lpc_domain_ops, priv); if (!priv->lpc_domain) { pr_err("Failed to create IRQ domain\n"); - goto free_irq_handle; + goto iounmap_base; } pch_lpc_reset(priv); =20 - fwspec.fwnode =3D parent->fwnode; - fwspec.param[0] =3D acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ; - fwspec.param[1] =3D IRQ_TYPE_LEVEL_HIGH; - fwspec.param_count =3D 2; - parent_irq =3D irq_create_fwspec_mapping(&fwspec); irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv); =20 pch_lpc_priv =3D priv; @@ -230,8 +217,6 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, =20 return 0; =20 -free_irq_handle: - irq_domain_free_fwnode(irq_handle); iounmap_base: iounmap(priv->base); free_priv: @@ -239,3 +224,34 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, =20 return -ENOMEM; } + +int __init pch_lpc_acpi_init(struct irq_domain *parent, + struct acpi_madt_lpc_pic *acpi_pchlpc) +{ + int parent_irq; + struct pch_lpc *priv; + struct irq_fwspec fwspec; + struct fwnode_handle *irq_handle; + int ret; + + irq_handle =3D irq_domain_alloc_named_fwnode("lpcintc"); + if (!irq_handle) { + pr_err("Unable to allocate domain handle\n"); + return -ENOMEM; + } + + fwspec.fwnode =3D parent->fwnode; + fwspec.param[0] =3D acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ; + fwspec.param[1] =3D IRQ_TYPE_LEVEL_HIGH; + fwspec.param_count =3D 2; + parent_irq =3D irq_create_fwspec_mapping(&fwspec); + + ret =3D pch_lpc_init(acpi_pchlpc->address, acpi_pchlpc->size, + irq_handle, parent_irq); + if (ret) { + irq_domain_free_fwnode(irq_handle); + return ret; + } + + return 0; +} --=20 2.52.0 From nobody Mon Feb 9 08:59:47 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 649602F60A3; Sat, 31 Jan 2026 09:46:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852778; cv=none; b=N2tTwnh7XkYUcRTUphVdIduZ2kaZ3Exj4S0WuYlLzvKGEHM7CsNRWHKUX1zk0s2xTPHAU5ws7SjhFVlDNgNAfNcdYPM6EHnbDVJiOkEh6+i+h25cagi5wfFkhdnvo1Qrnzfx4b6iPkH0IJ4Ofi/4MAVZHi1NlITX0xUQOn8anUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852778; c=relaxed/simple; bh=ZWkmJST26Se+Dq0sEKR+qMBuLWRCh23H5A3Ti+ZrnpY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nZo1gxmtatazOob931Qia0hKHpHUutHy543kPNovahDJI9BXl+nnmXqDAyGhtmDQZbu2aXrUpvQupE7O8IQ4en5Zspr8IEMM9P1Gv5mGisn8XuU9KNEzdNzBXLh4pvsVkwORX29vX/a4BHE2wGu24TUTFZrHI8IYFCZ8F/29njY= ARC-Authentication-Results: i=1; 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charset="utf-8" As OF-based initialization is going to be added to the driver, guard the ACPI-based initialization code with CONFIG_ACPI. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Icenowy Zheng Tested-by: Yao Zi --- drivers/irqchip/irq-loongson-pch-lpc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-l= oongson-pch-lpc.c index 4507000b991a6..96489e031d34e 100644 --- a/drivers/irqchip/irq-loongson-pch-lpc.c +++ b/drivers/irqchip/irq-loongson-pch-lpc.c @@ -225,6 +225,7 @@ static int __init pch_lpc_init(phys_addr_t addr, unsign= ed long size, return -ENOMEM; } =20 +#ifdef CONFIG_ACPI int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc) { @@ -255,3 +256,4 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, =20 return 0; } +#endif /* CONFIG_ACPI */ --=20 2.52.0 From nobody Mon Feb 9 08:59:47 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A90E33FE12; Sat, 31 Jan 2026 09:46:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852776; cv=none; b=mq2FZXhPDqhmAebXZSC7prasXbz6dUOnVHFd8myBSB6/H2vJFCMSrW5ojAZymkxu9iYPXKnpKTk+CpRqJEMpJPHJg3IliIKAJ3SmTbgpbb0KmwRwZZJVQZ59hm6xhPAJ7m56jrJ/sAH9rXS10uXi2Rei0jXRGMWy9Z9qe+bAxEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852776; c=relaxed/simple; bh=jmxURdJ/UF/4J4oKDQgJgN6DLn3C74LWfnmQNuu/FxA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z8gxA/+6RyVeOLDrRE+cOYLc5MCTiDqPIsMJ1nzxCo/xawNPcVnlkefALV7nS4zDDmOaRaeIVweglFhwtHKOJ28nS7UntlH3zK3BFzhb35vouaxwyT2XISRs/PGxysBjc9tB7VydUn7CpumIamGpy3TUqEBYDnoQn5EVArrsES8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.102.235]) by APP-05 (Coremail) with SMTP id zQCowAC3Sw9Rz31p9UgiBw--.57463S7; Sat, 31 Jan 2026 17:46:09 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Huacai Chen , Jiaxun Yang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Icenowy Zheng Subject: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code Date: Sat, 31 Jan 2026 17:45:44 +0800 Message-ID: <20260131094547.455916-6-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> References: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAC3Sw9Rz31p9UgiBw--.57463S7 X-Coremail-Antispam: 1UD129KBjvJXoW7tr13ZFy8Zr48Jr4kGrWrAFb_yoW8AF1DpF W5CayfAr4rGr129w1fCF18ArWayFs5GrW7trWxX3WfZw1DtrykGw1DCF1qvr4fArW3WFW5 uF4FgF45CFWUAF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUm214x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI IF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVF xhVjvjDU0xZFpf9x0JUQFxUUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" As the (kernel-internally) OF-based MIPS Loongson-3 systems can also have PCH LPC interrupt controller, add OF-based initialization code for the driver. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Icenowy Zheng Tested-by: Yao Zi --- drivers/irqchip/irq-loongson-pch-lpc.c | 28 ++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-l= oongson-pch-lpc.c index 96489e031d34e..0baa93028abf4 100644 --- a/drivers/irqchip/irq-loongson-pch-lpc.c +++ b/drivers/irqchip/irq-loongson-pch-lpc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include =20 #include "irq-loongson.h" @@ -257,3 +259,29 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, return 0; } #endif /* CONFIG_ACPI */ + +#ifdef CONFIG_OF +static int pch_lpc_of_init(struct device_node *node, + struct device_node *parent) +{ + int parent_irq; + struct fwnode_handle *irq_handle; + struct resource res; + + if (of_address_to_resource(node, 0, &res)) + return -EINVAL; + + parent_irq =3D irq_of_parse_and_map(node, 0); + if (!parent_irq) { + pr_err("Failed to get the parent IRQ for LPC IRQs\n"); + return -EINVAL; + } + + irq_handle =3D of_fwnode_handle(node); + + return pch_lpc_init(res.start, resource_size(&res), irq_handle, + parent_irq); +} + +IRQCHIP_DECLARE(pch_lpc, "loongson,pch-lpc-1.0", pch_lpc_of_init); +#endif /* CONFIG_OF */ --=20 2.52.0 From nobody Mon Feb 9 08:59:47 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D81633164BB; Sat, 31 Jan 2026 09:46:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852778; cv=none; b=MQ5jTUL9aLFHv4Nlw+iOCbzbuXrirO5C6qcjwJ7Z/Lw28PA0HDftH8ieK6W/5nuCasOeoWnHU4P6qjyt5oM1XdwKq0tirIeuglD0NGSdB+mfdYJTTPlggW/cGY+yd0O8Wrrlp9zI8RI2jKyCPPP4GfaP8sLyBnl0YDQfZRbzFAk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852778; c=relaxed/simple; bh=N5kK6S8PFSPQelD+YvhxuXEvoRW1SeFvBRq1h2RAgeA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u4jFE3NkSVLLw/Sa05lxv31nepqkcR2sfw2b3FA4ARypJDPoI0dYBjXFJq8Z3eyyGGrnVOtucJWqmLhIDwuYJQM2B/H6HLX7hxJjEWGmNpgYze46FD8gqaZ6K3tuiJNqFxAZUrIldOhSGkfdR/ICE403lml+8qSImGLeSep1KNo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.102.235]) by APP-05 (Coremail) with SMTP id zQCowAC3Sw9Rz31p9UgiBw--.57463S8; Sat, 31 Jan 2026 17:46:11 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Huacai Chen , Jiaxun Yang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Icenowy Zheng Subject: [PATCH 6/8] irqchip/loongson-pch-lpc: enable building on MIPS Loongson64 Date: Sat, 31 Jan 2026 17:45:45 +0800 Message-ID: <20260131094547.455916-7-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> References: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAC3Sw9Rz31p9UgiBw--.57463S8 X-Coremail-Antispam: 1UD129KBjvdXoW7XF4DKr18CF47Jw43Jr4fKrg_yoW3ArgEk3 4j9Fs7XFy2kry7JryrWF4fZry2kayqgrn2kF4Fqw1fX3WIqw1xW3Wjva15Jr47Ga48WFna v3yI9rn7Aw10yjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbv8FF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAVCq3wA2048vs2 IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28E F7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr 1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_ Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1V AY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAI cVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIx AIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2 KfnxnUUI43ZEXa7VUbPC7UUUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" As the driver can now support OF-based platforms, it's now possible to use it on MIPS Loongson64 machines. Drop the requirement of LOONGARCH for this driver, to allow build on both MIPS-based and LoongArch-based Loongson systems. Signed-off-by: Icenowy Zheng Tested-by: Yao Zi --- drivers/irqchip/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f334f49c9791f..80a3ec2fc2aed 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -754,7 +754,6 @@ config LOONGSON_PCH_MSI =20 config LOONGSON_PCH_LPC bool "Loongson PCH LPC Controller" - depends on LOONGARCH depends on MACH_LOONGSON64 default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY --=20 2.52.0 From nobody Mon Feb 9 08:59:47 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 008D9331203; Sat, 31 Jan 2026 09:46:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852780; cv=none; b=SfvQaLYvUuhIpRKTW4Ro9780+dTzBoSnEH57HJI3zYqAfQiKa2COziNTYDpdF9bdGOg0PThVLjHXBaoxoyT+ompiN6z9YEvB/A2XiopHiI7m4hVmzTyfmm1AI5pHQmV8l577SpAudyiJn/fm08PCWBoQtQ3Nv51s31jZYIa0tpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852780; c=relaxed/simple; bh=EbQzbvmvEwatvbIhtKPnEZppoLL1KfGMkI8JSBPO740=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Nsibvbmat92chpfpOPRAqqYpMft+OtnahaIvEgt13NtcRnTK06e1jMqITNWGAFDDL+CN9fHtYcnL8NQpSIcutj0MgMtNJyyPBF+/m1NEdRif5BB+EGecgOuiEPr0WJGgbKQ1FFzjwwhDKXwNHiH538TJILOiU2XFB0oT8tSqbAg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.102.235]) by APP-05 (Coremail) with SMTP id zQCowAC3Sw9Rz31p9UgiBw--.57463S9; Sat, 31 Jan 2026 17:46:12 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Huacai Chen , Jiaxun Yang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Icenowy Zheng Subject: [PATCH 7/8] MIPS: Loongson64: dts: sort nodes Date: Sat, 31 Jan 2026 17:45:46 +0800 Message-ID: <20260131094547.455916-8-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> References: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAC3Sw9Rz31p9UgiBw--.57463S9 X-Coremail-Antispam: 1UD129KBjvJXoWrZFy3Wr1ktr45Aw1fAr48Xrb_yoW8JrWfpw srA3929r4FgFnIyrnYqFyrJF4fAFZYyFyDuFs2yrW7J3sYq3Wjvr1xGFyrtF9rWrWrZ34j grn7t34jkF1xuw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmI14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCw CI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnI WIevJa73UjIFyTuYvjfUOyIUUUUUU X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" The RTC's address is after UARTs, however the node is currently before them. Re-order the node to match address sequence. Signed-off-by: Icenowy Zheng Tested-by: Yao Zi --- arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts= /loongson/ls7a-pch.dtsi index ee71045883e7e..5269bf0f789b0 100644 --- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi @@ -19,13 +19,6 @@ pic: interrupt-controller@10000000 { #interrupt-cells =3D <2>; }; =20 - rtc0: rtc@100d0100 { - compatible =3D "loongson,ls7a-rtc"; - reg =3D <0 0x100d0100 0 0x78>; - interrupt-parent =3D <&pic>; - interrupts =3D <52 IRQ_TYPE_LEVEL_HIGH>; - }; - ls7a_uart0: serial@10080000 { compatible =3D "ns16550a"; reg =3D <0 0x10080000 0 0x100>; @@ -65,6 +58,13 @@ ls7a_uart3: serial@10080300 { no-loopback-test; }; =20 + rtc0: rtc@100d0100 { + compatible =3D "loongson,ls7a-rtc"; + reg =3D <0 0x100d0100 0 0x78>; + interrupt-parent =3D <&pic>; + interrupts =3D <52 IRQ_TYPE_LEVEL_HIGH>; + }; + pci@1a000000 { compatible =3D "loongson,ls7a-pci"; device_type =3D "pci"; --=20 2.52.0 From nobody Mon Feb 9 08:59:47 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BF2833C524; Sat, 31 Jan 2026 09:46:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852781; cv=none; b=nMwrF2dkmcg5r2VZ6DMxaZMavtjksTQ4x98eoi5RA1OnRrPyCj0EmFJDMs9nHCXguGCRd1tAga6Htn9N7I0/T/Zbv0ZLxIq7lWcSzTzREZX3PGF5YIsNP65lbhAFRIJxdpJQJviu6FhMRmKh1K9pv/YD/x24NqT7+KMVGCxJoso= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852781; c=relaxed/simple; bh=q09QYvq+S2qlBAVxztGJqBEV+PIXyFtWRAbvlaoK/D8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GAcUYNguVVCDDjvr2qKznKoHhl3DJy5ZoT0yAdFjxev/C5bd4MA/lPTc6XfiiDCqrcfLysGb/T4+hKqvYniQkB6JvF/AdCjd17pYDZ6YYo/24SxaBCgYTIlZMNZ+TtmNubOt+8JGZf8P3LO7gygFOoHhW5LXhEiziO0y8WwtGm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.102.235]) by APP-05 (Coremail) with SMTP id zQCowAC3Sw9Rz31p9UgiBw--.57463S10; Sat, 31 Jan 2026 17:46:13 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Huacai Chen , Jiaxun Yang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Icenowy Zheng Subject: [PATCH 8/8] MIPS: Loongson64: dts: add node for LS7A PCH LPC Date: Sat, 31 Jan 2026 17:45:47 +0800 Message-ID: <20260131094547.455916-9-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> References: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAC3Sw9Rz31p9UgiBw--.57463S10 X-Coremail-Antispam: 1UD129KBjvdXoW7Xw47JryxCrWftrWkGF17KFg_yoWftFg_Ar 17Ka1rWrZ3AasFy34kZrWkCFy7Z3y7A3s3C3W2gr15XF9YyrnxGFWUZ3yUAF1fWrWYqr1r t39Yqr4DCF4IkjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbvAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAVCq3wA2048vs2 IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28E F7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8Jr0_Cr 1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVW8Jr0_Cr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCw CI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUvcSsG vfC2KfnxnUUI43ZEXa7VUbPC7UUUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Loongson 7A series PCH contain a LPC IRQ controller. Add the device tree node of it. Signed-off-by: Icenowy Zheng Tested-by: Yao Zi --- arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts= /loongson/ls7a-pch.dtsi index 5269bf0f789b0..03018db47b18c 100644 --- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi @@ -19,6 +19,15 @@ pic: interrupt-controller@10000000 { #interrupt-cells =3D <2>; }; =20 + lpc: interrupt-controller@10002000 { + compatible =3D "loongson,pch-lpc-1.0"; + reg =3D <0 0x10002000 0 0x1000>; + interrupt-controller; + interrupt-parent =3D <&pic>; + interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells =3D <2>; + }; + ls7a_uart0: serial@10080000 { compatible =3D "ns16550a"; reg =3D <0 0x10080000 0 0x100>; --=20 2.52.0