To configure the video PLLs and enable the video GDSCs on SM8250,
platform, the MX rail must be ON along with MMCX. Split the bindings
file in order to provide separate file utilizing MMCX and MX power
domains.
Fixes: dafb992a95e1 ("dt-bindings: clock: add SM8250 QCOM video clock bindings")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../bindings/clock/qcom,sm8250-videocc.yaml | 80 ++++++++++++++++++++++
.../devicetree/bindings/clock/qcom,videocc.yaml | 20 ------
2 files changed, 80 insertions(+), 20 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8250-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8250-videocc.yaml
new file mode 100644
index 000000000000..94264c309c65
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8250-videocc.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8250-videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller
+
+maintainers:
+ - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+ Qualcomm video clock control module provides the clocks, resets and power
+ domains on Qualcomm SoCs.
+
+ See also::
+ include/dt-bindings/clock/qcom,videocc-sm8250.h
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - qcom,sm8250-videocc
+
+ clocks:
+ items:
+ - description: AHB
+ - description: Board XO source
+ - description: Board active XO source
+ clock-names:
+ items:
+ - const: iface
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+
+ power-domains:
+ items:
+ - description:
+ A phandle and PM domain specifier for the MMCX power domain.
+ - description:
+ A phandle and PM domain specifier for the MX power domain.
+
+ required-opps:
+ items:
+ - description:
+ A phandle to an OPP node describing required MMCX performance point.
+ - description:
+ A phandle to an OPP node describing required MX performance point.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - '#power-domain-cells'
+ - power-domains
+ - required-opps
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@ab00000 {
+ compatible = "qcom,sm8250-videocc";
+ reg = <0x0ab00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MX>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
index f4ff9acef9d5..8676c7e22b4c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -19,7 +19,6 @@ description: |
include/dt-bindings/clock/qcom,videocc-sc7280.h
include/dt-bindings/clock/qcom,videocc-sdm845.h
include/dt-bindings/clock/qcom,videocc-sm8150.h
- include/dt-bindings/clock/qcom,videocc-sm8250.h
properties:
compatible:
@@ -30,7 +29,6 @@ properties:
- qcom,sdm845-videocc
- qcom,sm6350-videocc
- qcom,sm8150-videocc
- - qcom,sm8250-videocc
- items:
- const: qcom,sc8180x-videocc
- const: qcom,sm8150-videocc
@@ -128,24 +126,6 @@ allOf:
- const: iface
- const: bi_tcxo
- - if:
- properties:
- compatible:
- enum:
- - qcom,sm8250-videocc
- then:
- properties:
- clocks:
- items:
- - description: AHB
- - description: Board XO source
- - description: Board active XO source
- clock-names:
- items:
- - const: iface
- - const: bi_tcxo
- - const: bi_tcxo_ao
-
unevaluatedProperties: false
examples:
--
2.47.3
On Sat, 31 Jan 2026 19:33:43 +0200, Dmitry Baryshkov wrote:
> To configure the video PLLs and enable the video GDSCs on SM8250,
> platform, the MX rail must be ON along with MMCX. Split the bindings
> file in order to provide separate file utilizing MMCX and MX power
> domains.
>
> Fixes: dafb992a95e1 ("dt-bindings: clock: add SM8250 QCOM video clock bindings")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> .../bindings/clock/qcom,sm8250-videocc.yaml | 80 ++++++++++++++++++++++
> .../devicetree/bindings/clock/qcom,videocc.yaml | 20 ------
> 2 files changed, 80 insertions(+), 20 deletions(-)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8250-videocc.example.dtb: clock-controller@ab00000 (qcom,sm8250-videocc): clock-names:0: 'iface' was expected
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8250-videocc.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8250-videocc.example.dtb: clock-controller@ab00000 (qcom,sm8250-videocc): clock-names: ['bi_tcxo'] is too short
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8250-videocc.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8250-videocc.example.dtb: clock-controller@ab00000 (qcom,sm8250-videocc): clocks: [[4294967295, 0]] is too short
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8250-videocc.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260131-iris-venus-fix-sm8250-v1-1-b635ee66284c@oss.qualcomm.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
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