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[PATCH 0/2] Fix a __clk_core_init parental issue

Nicolas Frattaroli posted 2 patches 1 week, 3 days ago 
drivers/clk/clk.c            | 6 +++---
drivers/clk/imx/clk-imx8mp.c | 4 +++-
drivers/clk/imx/clk.h        | 4 ++++
3 files changed, 10 insertions(+), 4 deletions(-)
[PATCH 0/2] Fix a __clk_core_init parental issue
Posted by Nicolas Frattaroli 1 week, 3 days ago 
Mark and Alexander, please test to see if these patches resolve the
issues on your boards.

I expect the first patch to completely fix the problem on the Avenger96
(STM32MP1) board.

I'm less sure about the i.MX8MP board. I believe the second patch is
needed there, but I don't know for certain, as I don't have the hardware
to test.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Nicolas Frattaroli (2):
      clk: Disable CLK_OPS_PARENT_ENABLED parent only after CRITICAL check
      clk: imx8mp: Mark arm_a53_div as critical

 drivers/clk/clk.c            | 6 +++---
 drivers/clk/imx/clk-imx8mp.c | 4 +++-
 drivers/clk/imx/clk.h        | 4 ++++
 3 files changed, 10 insertions(+), 4 deletions(-)
---
base-commit: c099ccb60bc99900dd54ac22d7e68b8e56f15e4b
change-id: 20260128-ops-parent-enable-fix-65ee4977cbd3

Best regards,
-- 
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Re: [PATCH 0/2] Fix a __clk_core_init parental issue
Posted by Mark Brown 1 week, 3 days ago 
On Wed, Jan 28, 2026 at 07:38:49PM +0100, Nicolas Frattaroli wrote:
> Mark and Alexander, please test to see if these patches resolve the
> issues on your boards.
> 
> I expect the first patch to completely fix the problem on the Avenger96
> (STM32MP1) board.

This gets further but still fails on Avenger96, looks like we've got
more clocks need work:

[    0.513739] __clk_core_init: enabling parent pll3_q for spi1_k
[    0.519521] __clk_core_init: disabling parent pll3_q for spi1_k
[    0.525489] __clk_core_init: enabling parent pll3_q for spi2_k
[    0.531311] __clk_core_init: disabling parent pll3_q for spi2_k
[    0.537275] __clk_core_init: enabling parent pll3_q for spi3_k
[    0.543101] __clk_core_init: disabling parent pll3_q for spi3_k
[    0.549066] __clk_core_init: enabling parent ck_hsi for spi4_k
[    0.554894] __clk_core_init: disabling parent ck�
U-Boot SPL 2023.07.02-dh-stm32mp1-dhcor-avenger96-20230727.02 (Jul 11 2023 - 15:20:44 +0000)

   https://lava.sirena.org.uk/scheduler/job/2413747#L593
Re: [PATCH 0/2] Fix a __clk_core_init parental issue
Posted by Alexander Stein 1 week, 2 days ago 
Am Mittwoch, 28. Januar 2026, 21:17:09 CET schrieb Mark Brown:
> On Wed, Jan 28, 2026 at 07:38:49PM +0100, Nicolas Frattaroli wrote:
> > Mark and Alexander, please test to see if these patches resolve the
> > issues on your boards.
> > 
> > I expect the first patch to completely fix the problem on the Avenger96
> > (STM32MP1) board.
> 
> This gets further but still fails on Avenger96, looks like we've got
> more clocks need work:
> 
> [    0.513739] __clk_core_init: enabling parent pll3_q for spi1_k
> [    0.519521] __clk_core_init: disabling parent pll3_q for spi1_k
> [    0.525489] __clk_core_init: enabling parent pll3_q for spi2_k
> [    0.531311] __clk_core_init: disabling parent pll3_q for spi2_k
> [    0.537275] __clk_core_init: enabling parent pll3_q for spi3_k
> [    0.543101] __clk_core_init: disabling parent pll3_q for spi3_k
> [    0.549066] __clk_core_init: enabling parent ck_hsi for spi4_k
> [    0.554894] __clk_core_init: disabling parent ck�
> U-Boot SPL 2023.07.02-dh-stm32mp1-dhcor-avenger96-20230727.02 (Jul 11 2023 - 15:20:44 +0000)
> 
>    https://lava.sirena.org.uk/scheduler/job/2413747#L593
> 

I also got more clocks in the list, but it still hangs eventually:
[    1.453206] __clk_core_init: enabling parent audio_pll1_out for clkout1_sel
[    1.458095] __clk_core_init: disabling parent audio_pll1_out for clkout1_sel
[    1.464684] __clk_core_init: enabling parent audio_pll1_out for clkout2_sel
[    1.472174] __clk_core_init: disabling parent audio_pll1_out for clkout2_sel
[    1.478784] __clk_core_init: enabling parent sys_pll2_500m for arm_a53_div
[    1.485679] __clk_core_init: disabling parent sys_pll2_500m for arm_a53_div
[    1.492675] __clk_core_init: enabling parent sys_pll2_200m for m7_core
[    1.499233] __clk_core_init: disabling parent sys_pll2_200m for m7_core
[    1.505888] __clk_core_init: enabling parent osc_24m for ml_core
[    1.511924] __clk_core_init: disabling parent osc_24m for ml_core
[    1.518050] __clk_core_init: enabling parent osc_24m for gpu3d_core
[    1.524344] __clk_core_init: disabling parent osc_24m for gpu3d_core
[    1.530738] __clk_core_init: enabling parent osc_24m for gpu3d_shader_core
[    1.537646] __clk_core_init: disabling parent osc_24m for gpu3d_shader_core
[    1.544655] __clk_core_init: enabling parent osc_24m for gpu2d_core
[    1.550945] __clk_core_init: disabling parent osc_24m for gpu2d_core
[    1.557341] __clk_core_init: enabling parent osc_24m for audio_axi
[    1.563551] __clk_core_init: disabling parent osc_24m for audio_axi
[    1.569863] __clk_core_init: enabling parent sys_pll1_800m for hsio_axi
[    1.576507] __clk_core_init: disabling parent sys_pll1_800m for hsio_axi

Best regards,
Alexander
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