From nobody Sun Feb 8 01:31:08 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9785737105F; Wed, 28 Jan 2026 18:40:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769625612; cv=pass; b=suJTf9Iq7chIYyVORWVsp1vnzOaaof63DqHRpq/c/0Ufx7PNhIaJYNc5P59pxq2R7VIkHBM+4dR0Qka+f8x0JwPBRyUgRWo9rx8gNMia1CxzFbgEcLKEsrGqufhByPofKZ2/iSRYfSu/s8fVi39gSG7JbOvB9TxwKTHVnxlecq8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769625612; c=relaxed/simple; bh=OAdFrquKGDp7XiFTYgdbCRkM6pgcnhMKBE/waj03ZcY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UBKUaLmmeys2PrbpuoqxBY2clYV/erEG5TG9bWwfBlbbJDwpg6B5VJZBM4Z4/UbgXN8dHYlNsOr1LNqZ5LogV9HDAUdIB7WenBsSfW9ktU9vMnGXAOrrTHJ05c4GLhpdXCiz6Fw4M1ET6fhDfLgv0U2m3wrYK5PtU/kUTXKOfAc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=IrlW0Kai; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="IrlW0Kai" ARC-Seal: i=1; a=rsa-sha256; t=1769625579; cv=none; d=zohomail.com; s=zohoarc; b=KbAx9IzY0rH4cAFTkoJqpMnfyC15wZ/HtckXt5ZSLOIywlF6f4efzb70C42alVDrV8KfiK3A0GftAwqlvY2BLZXXC14TWsP80rD/32IaC6au2J6T8/Tg5K44RQdNrfBmlVF5uv+noJCIOosA9JkNFWzxRpapGK6zZNjMJ52EDog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769625579; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZkPh6rEGGj5EfY6a9YgmvYuB+fZaCezIbVUYx4CZTr4=; b=RwQYRfKeJrKWZC5OiVk2X5cu16M9KcM7e0R1NcUs6np2RzQOtruFFnoxTb2a/BcZnn9ZaBTv1MhHHIykB2xvyu7U4B+JdYHSdzzqDoPsY4K+8wmxUj5rhwyWqHckZyDlpLvXTKcEZpX2zv3f5T9Z1Tb1RZrk2WlzTVYRUuGQ72k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1769625579; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=ZkPh6rEGGj5EfY6a9YgmvYuB+fZaCezIbVUYx4CZTr4=; b=IrlW0KairsALp3RcHiCJWnsIOZrLuPIuFBPhO04FIYnIXIwStOza0Rcyxl8D59ZX 0xerhfmizOxka/AQcywYOvnnG8egqgwb6M5obCLhAMQImhYSoL/RjpbftK5fENTXAoN qEXyTP8XeyEXWXXtUoIJ8Bielo/N5jyBzfa6cfeI= Received: by mx.zohomail.com with SMTPS id 176962557768244.502411600919686; Wed, 28 Jan 2026 10:39:37 -0800 (PST) From: Nicolas Frattaroli Date: Wed, 28 Jan 2026 19:38:50 +0100 Subject: [PATCH 1/2] clk: Disable CLK_OPS_PARENT_ENABLED parent only after CRITICAL check Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ops-parent-enable-fix-v1-1-ff39cc37f98d@collabora.com> References: <20260128-ops-parent-enable-fix-v1-0-ff39cc37f98d@collabora.com> In-Reply-To: <20260128-ops-parent-enable-fix-v1-0-ff39cc37f98d@collabora.com> To: Mark Brown , Alexander Stein , Michael Turquette , Stephen Boyd , AngeloGioacchino Del Regno , Chen-Yu Tsai , Abel Vesa , Peng Fan , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@collabora.com, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The call to clk_core_enable_lock done by __clk_core_init after checking the clock flags for CLK_IS_CRITICAL enables the parent clock. In Commit 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc"), the parent gets disabled before this check, if the flag CLK_OPS_PARENT_ENABLED is set on the clock. This results in a situation where critical clocks have their parent briefly disabled, which kills the system. Fix this by moving the balancing operation to after the CLK_IS_CRITICAL check, which should resolve the problem. Fixes: 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc") Reported-by: Mark Brown Closes: https://lore.kernel.org/r/036da7ce-6487-4a6e-9b15-97c6d3bcdcec@sire= na.org.uk/ Signed-off-by: Nicolas Frattaroli --- drivers/clk/clk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 1b0f9d567f48..8f5ef9ce77d2 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -4056,9 +4056,6 @@ static int __clk_core_init(struct clk_core *core) rate =3D 0; core->rate =3D core->req_rate =3D rate; =20 - if (core->flags & CLK_OPS_PARENT_ENABLE) - clk_core_disable_unprepare(core->parent); - /* * Enable CLK_IS_CRITICAL clocks so newly added critical clocks * don't get accidentally disabled when walking the orphan tree and @@ -4081,6 +4078,9 @@ static int __clk_core_init(struct clk_core *core) } } =20 + if (core->flags & CLK_OPS_PARENT_ENABLE) + clk_core_disable_unprepare(core->parent); + clk_core_reparent_orphans_nolock(); out: clk_pm_runtime_put(core); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ops-parent-enable-fix-v1-2-ff39cc37f98d@collabora.com> References: <20260128-ops-parent-enable-fix-v1-0-ff39cc37f98d@collabora.com> In-Reply-To: <20260128-ops-parent-enable-fix-v1-0-ff39cc37f98d@collabora.com> To: Mark Brown , Alexander Stein , Michael Turquette , Stephen Boyd , AngeloGioacchino Del Regno , Chen-Yu Tsai , Abel Vesa , Peng Fan , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@collabora.com, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 It appears the i.MX8MP does not like when arm_a53_div, or rather the parent it depends on, sys_pll2_500m, is briefly turned off during __clk_core_init. In the past, this clock driver could get away with not declaring the clock as critical, as nothing ever fiddled with its parent that early on. However, after Commit 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc"), this changed. In order to guarantee that it keeps its parent enabled during __clk_core_init if it sets the flag CLK_OPS_PARENT_ENABLE, the clock must be marked as critical. Fixes: 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc") Reported-by: Alexander Stein Closes: https://lore.kernel.org/r/6239343.lOV4Wx5bFT@steina-w/ Signed-off-by: Nicolas Frattaroli --- drivers/clk/imx/clk-imx8mp.c | 4 +++- drivers/clk/imx/clk.h | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index fe6dac70f1a1..ee10f845faff 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -655,7 +655,9 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) hws[IMX8MP_CLK_CLKOUT2_DIV] =3D imx_clk_hw_divider("clkout2_div", "clkout= 2_sel", anatop_base + 0x128, 16, 4); hws[IMX8MP_CLK_CLKOUT2] =3D imx_clk_hw_gate("clkout2", "clkout2_div", ana= top_base + 0x128, 24); =20 - hws[IMX8MP_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core("arm_a53_div", im= x8mp_a53_sels, ccm_base + 0x8000); + hws[IMX8MP_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core_critical("arm_a53= _div", + imx8mp_a53_sels, + ccm_base + 0x8000); hws[IMX8MP_CLK_A53_SRC] =3D hws[IMX8MP_CLK_A53_DIV]; hws[IMX8MP_CLK_A53_CG] =3D hws[IMX8MP_CLK_A53_DIV]; hws[IMX8MP_CLK_M7_CORE] =3D imx8m_clk_hw_composite_core("m7_core", imx8mp= _m7_sels, ccm_base + 0x8080); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..97cac1d623ca 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -454,6 +454,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *na= me, _imx8m_clk_hw_composite(name, parent_names, reg, \ IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) =20 +#define imx8m_clk_hw_composite_core_critical(name, parent_names, reg) \ + _imx8m_clk_hw_composite(name, parent_names, reg, \ + IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) + #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \ _imx8m_clk_hw_composite(name, parent_names, reg, \ IMX_COMPOSITE_FW_MANAGED, \ --=20 2.52.0