Some QCS8300 interconnect nodes have QoS registers located inside
a block whose interface is clock-gated. For those nodes, driver
must enable the corresponding clock(s) before accessing the
registers. Add the 'clocks' property so the driver can obtain
and enable the required clock(s).
Only interconnects that have clock‑gated QoS register interface
use this property; it is not applicable to all interconnect nodes.
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
---
.../interconnect/qcom,qcs8300-rpmh.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml
index e9f528d6d9a8..88fe17277110 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml
@@ -35,6 +35,10 @@ properties:
reg:
maxItems: 1
+ clocks:
+ minItems: 1
+ maxItems: 4
+
required:
- compatible
@@ -54,6 +58,64 @@ allOf:
required:
- reg
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs8300-aggre1-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS PHY AXI clock
+ - description: aggre QUP PRIM AXI clock
+ - description: aggre USB2 PRIM AXI clock
+ - description: aggre USB3 PRIM AXI clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs8300-aggre2-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: RPMH CC IPA clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs8300-gem-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: GCC DDRSS GPU AXI clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs8300-clk-virt
+ - qcom,qcs8300-config-noc
+ - qcom,qcs8300-dc-noc
+ - qcom,qcs8300-gpdsp-anoc
+ - qcom,qcs8300-lpass-ag-noc
+ - qcom,qcs8300-mc-virt
+ - qcom,qcs8300-mmss-noc
+ - qcom,qcs8300-nspa-noc
+ - qcom,qcs8300-pcie-anoc
+ - qcom,qcs8300-system-noc
+ then:
+ properties:
+ clocks: false
+
unevaluatedProperties: false
examples:
@@ -63,6 +125,7 @@ examples:
reg = <0x9100000 0xf7080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc_ddrss_gpu_axi_clk>;
};
clk_virt: interconnect-0 {
--
2.43.0
On Tue, Jan 27, 2026 at 02:31:14PM +0530, Odelu Kukatla wrote: > Some QCS8300 interconnect nodes have QoS registers located inside > a block whose interface is clock-gated. For those nodes, driver > must enable the corresponding clock(s) before accessing the > registers. Add the 'clocks' property so the driver can obtain > and enable the required clock(s). > > Only interconnects that have clock‑gated QoS register interface > use this property; it is not applicable to all interconnect nodes. > > Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> > --- > .../interconnect/qcom,qcs8300-rpmh.yaml | 63 +++++++++++++++++++ > 1 file changed, 63 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Best regards, Krzysztof
On 1/27/26 10:01 AM, Odelu Kukatla wrote: > Some QCS8300 interconnect nodes have QoS registers located inside > a block whose interface is clock-gated. For those nodes, driver > must enable the corresponding clock(s) before accessing the > registers. Add the 'clocks' property so the driver can obtain > and enable the required clock(s). > > Only interconnects that have clock‑gated QoS register interface > use this property; it is not applicable to all interconnect nodes. > > Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> > --- [...] > + - description: aggre UFS PHY AXI clock > + - description: aggre QUP PRIM AXI clock > + - description: aggre USB2 PRIM AXI clock > + - description: aggre USB3 PRIM AXI clock LeMans has one more USB3 clock here, but it also happens to have 1 more USB3 host, so that checks out > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,qcs8300-aggre2-noc > + then: > + properties: > + clocks: > + items: > + - description: RPMH CC IPA clock LeMans also has ufscard clk here > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,qcs8300-gem-noc > + then: > + properties: > + clocks: > + items: > + - description: GCC DDRSS GPU AXI clock and lacks this one Are there actual reasons for these differences? Konrad
On 1/27/2026 4:24 PM, Konrad Dybcio wrote: > On 1/27/26 10:01 AM, Odelu Kukatla wrote: >> Some QCS8300 interconnect nodes have QoS registers located inside >> a block whose interface is clock-gated. For those nodes, driver >> must enable the corresponding clock(s) before accessing the >> registers. Add the 'clocks' property so the driver can obtain >> and enable the required clock(s). >> >> Only interconnects that have clock‑gated QoS register interface >> use this property; it is not applicable to all interconnect nodes. >> >> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> >> --- > > [...] > >> + - description: aggre UFS PHY AXI clock >> + - description: aggre QUP PRIM AXI clock >> + - description: aggre USB2 PRIM AXI clock >> + - description: aggre USB3 PRIM AXI clock > > LeMans has one more USB3 clock here, but it also happens to have > 1 more USB3 host, so that checks out > Thanks for the review, Konrad! On aggre1 noc, QCS8300 has only a single USB3 path, which corresponds to the clock in the binding. LeMans includes an additional USB3 host block, and therefore has an extra USB3 related clock that QCS8300 does not have. The difference reflects a real hardware variation between the two platforms. >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,qcs8300-aggre2-noc >> + then: >> + properties: >> + clocks: >> + items: >> + - description: RPMH CC IPA clock > > LeMans also has ufscard clk here > For aggre2 noc, QCS8300 does not integrate the ufscard controller present on LeMans, so that clock is not part of the QCS8300 hardware. The only QoS relevant clock on this node for QCS8300 is the RPMH CC IPA clock, which is why only that one appears in the binding. >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,qcs8300-gem-noc >> + then: >> + properties: >> + clocks: >> + items: >> + - description: GCC DDRSS GPU AXI clock > > and lacks this one > > Are there actual reasons for these differences? > The gem noc QoS interface on QCS8300 requires the DDRSS GPU AXI clock to be enabled for QoS register access, so it is listed in the binding. The difference is therefore due to SoC level differences. Thanks, Odelu > Konrad
On 1/29/26 11:10 AM, Odelu Kukatla wrote: > > > On 1/27/2026 4:24 PM, Konrad Dybcio wrote: >> On 1/27/26 10:01 AM, Odelu Kukatla wrote: >>> Some QCS8300 interconnect nodes have QoS registers located inside >>> a block whose interface is clock-gated. For those nodes, driver >>> must enable the corresponding clock(s) before accessing the >>> registers. Add the 'clocks' property so the driver can obtain >>> and enable the required clock(s). >>> >>> Only interconnects that have clock‑gated QoS register interface >>> use this property; it is not applicable to all interconnect nodes. >>> >>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> >>> --- [...] >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - qcom,qcs8300-aggre2-noc >>> + then: >>> + properties: >>> + clocks: >>> + items: >>> + - description: RPMH CC IPA clock >> >> LeMans also has ufscard clk here >> > > For aggre2 noc, QCS8300 does not integrate the ufscard controller > present on LeMans, so that clock is not part of the QCS8300 hardware. > The only QoS relevant clock on this node for QCS8300 is the RPMH CC IPA > clock, which is why only that one appears in the binding. Ohhh I forgot UFSCard translated to UFS1.. >>> + >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - qcom,qcs8300-gem-noc >>> + then: >>> + properties: >>> + clocks: >>> + items: >>> + - description: GCC DDRSS GPU AXI clock >> >> and lacks this one >> >> Are there actual reasons for these differences? >> > > The gem noc QoS interface on QCS8300 requires the DDRSS GPU AXI clock to > be enabled for QoS register access, so it is listed in the binding. The > difference is therefore due to SoC level differences. Alright, thanks Konrad
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