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Tue, 27 Jan 2026 01:01:49 -0800 (PST) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8231873bf53sm11579228b3a.45.2026.01.27.01.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 01:01:48 -0800 (PST) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH v2 1/3] dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoS Date: Tue, 27 Jan 2026 14:31:14 +0530 Message-ID: <20260127090116.1438780-2-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260127090116.1438780-1-odelu.kukatla@oss.qualcomm.com> References: <20260127090116.1438780-1-odelu.kukatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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For those nodes, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock=E2=80=91gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Odelu Kukatla Reviewed-by: Krzysztof Kozlowski --- .../interconnect/qcom,qcs8300-rpmh.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rp= mh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.= yaml index e9f528d6d9a8..88fe17277110 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml @@ -35,6 +35,10 @@ properties: reg: maxItems: 1 =20 + clocks: + minItems: 1 + maxItems: 4 + required: - compatible =20 @@ -54,6 +58,64 @@ allOf: required: - reg =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre QUP PRIM AXI clock + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-gem-noc + then: + properties: + clocks: + items: + - description: GCC DDRSS GPU AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-clk-virt + - qcom,qcs8300-config-noc + - qcom,qcs8300-dc-noc + - qcom,qcs8300-gpdsp-anoc + - qcom,qcs8300-lpass-ag-noc + - qcom,qcs8300-mc-virt + - qcom,qcs8300-mmss-noc + - qcom,qcs8300-nspa-noc + - qcom,qcs8300-pcie-anoc + - qcom,qcs8300-system-noc + then: + properties: + clocks: false + unevaluatedProperties: false =20 examples: @@ -63,6 +125,7 @@ examples: reg =3D <0x9100000 0xf7080>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc_ddrss_gpu_axi_clk>; }; =20 clk_virt: interconnect-0 { --=20 2.43.0