Mahua is a derivative of the Glymur SoC. This patch extends the
Glymur driver to support Mahua by:
1. Adding new node definitions for interconnects that differ from Glymur
(Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
2. Reusing existing Glymur definitions for identical NoCs.
3. Overriding the channel and buswidth, with Mahua specific values for
the differing NoCs
Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
drivers/interconnect/qcom/glymur.c | 153 ++++++++++++++++++++++++++++++++++++-
1 file changed, 152 insertions(+), 1 deletion(-)
diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom/glymur.c
index e5c07795a6c67ab8a59daf2fc4b8a5fa6dd014d6..65b03b2d5cdc69df0d54e209aed9c8e90309f577 100644
--- a/drivers/interconnect/qcom/glymur.c
+++ b/drivers/interconnect/qcom/glymur.c
@@ -9,6 +9,7 @@
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/of_platform.h>
+#include <linux/property.h>
#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
#include "bcm-voter.h"
@@ -2040,6 +2041,60 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
+static struct qcom_icc_node * const mahua_cnoc_cfg_nodes[] = {
+ [MASTER_CNOC_CFG] = &qsm_cfg,
+ [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
+ [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
+ [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
+ [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
+ [SLAVE_AV1_ENC_CFG] = &qhs_av1_enc_cfg,
+ [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
+ [SLAVE_CLK_CTL] = &qhs_clk_ctl,
+ [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
+ [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
+ [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+ [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
+ [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
+ [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg,
+ [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg,
+ [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg,
+ [SLAVE_PCIE_5_CFG] = &qhs_pcie5_cfg,
+ [SLAVE_PCIE_6_CFG] = &qhs_pcie6_cfg,
+ [SLAVE_PCIE_RSCC] = &qhs_pcie_rscc,
+ [SLAVE_PDM] = &qhs_pdm,
+ [SLAVE_PRNG] = &qhs_prng,
+ [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
+ [SLAVE_QSPI_0] = &qhs_qspi,
+ [SLAVE_QUP_0] = &qhs_qup0,
+ [SLAVE_QUP_1] = &qhs_qup1,
+ [SLAVE_QUP_2] = &qhs_qup2,
+ [SLAVE_SDCC_2] = &qhs_sdc2,
+ [SLAVE_SDCC_4] = &qhs_sdc4,
+ [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg,
+ [SLAVE_TCSR] = &qhs_tcsr,
+ [SLAVE_TLMM] = &qhs_tlmm,
+ [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+ [SLAVE_USB2] = &qhs_usb2_0_cfg,
+ [SLAVE_USB3_0] = &qhs_usb3_0_cfg,
+ [SLAVE_USB3_1] = &qhs_usb3_1_cfg,
+ [SLAVE_USB3_2] = &qhs_usb3_2_cfg,
+ [SLAVE_USB3_MP] = &qhs_usb3_mp_cfg,
+ [SLAVE_USB4_0] = &qhs_usb4_0_cfg,
+ [SLAVE_USB4_1] = &qhs_usb4_1_cfg,
+ [SLAVE_USB4_2] = &qhs_usb4_2_cfg,
+ [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
+ [SLAVE_CNOC_PCIE_SLAVE_EAST_CFG] = &qss_cnoc_pcie_slave_east_cfg,
+ [SLAVE_CNOC_PCIE_SLAVE_WEST_CFG] = &qss_cnoc_pcie_slave_west_cfg,
+ [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg,
+ [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
+ [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
+ [SLAVE_PCIE_EAST_ANOC_CFG] = &qss_pcie_east_anoc_cfg,
+ [SLAVE_PCIE_WEST_ANOC_CFG] = &qss_pcie_west_anoc_cfg,
+ [SLAVE_QDSS_STM] = &xs_qdss_stm,
+ [SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
static const struct regmap_config glymur_cnoc_cfg_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -2056,6 +2111,14 @@ static const struct qcom_icc_desc glymur_cnoc_cfg = {
.num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
};
+static const struct qcom_icc_desc mahua_cnoc_cfg = {
+ .config = &glymur_cnoc_cfg_regmap_config,
+ .nodes = mahua_cnoc_cfg_nodes,
+ .num_nodes = ARRAY_SIZE(mahua_cnoc_cfg_nodes),
+ .bcms = cnoc_cfg_bcms,
+ .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
+};
+
static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
&bcm_cn0,
};
@@ -2115,6 +2178,27 @@ static struct qcom_icc_node * const hscnoc_nodes[] = {
[SLAVE_PCIE_WEST] = &qns_pcie_west,
};
+static struct qcom_icc_node * const mahua_hscnoc_nodes[] = {
+ [MASTER_GPU_TCU] = &alm_gpu_tcu,
+ [MASTER_PCIE_TCU] = &alm_pcie_qtc,
+ [MASTER_SYS_TCU] = &alm_sys_tcu,
+ [MASTER_APPSS_PROC] = &chm_apps,
+ [MASTER_AGGRE_NOC_EAST] = &qnm_aggre_noc_east,
+ [MASTER_GFX3D] = &qnm_gpu,
+ [MASTER_LPASS_GEM_NOC] = &qnm_lpass,
+ [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
+ [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
+ [MASTER_COMPUTE_NOC] = &qnm_nsp_noc,
+ [MASTER_PCIE_EAST] = &qnm_pcie_east,
+ [MASTER_PCIE_WEST] = &qnm_pcie_west,
+ [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+ [MASTER_GIC] = &xm_gic,
+ [SLAVE_HSCNOC_CNOC] = &qns_hscnoc_cnoc,
+ [SLAVE_LLCC] = &qns_llcc,
+ [SLAVE_PCIE_EAST] = &qns_pcie_east,
+ [SLAVE_PCIE_WEST] = &qns_pcie_west,
+};
+
static const struct regmap_config glymur_hscnoc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -2131,6 +2215,14 @@ static const struct qcom_icc_desc glymur_hscnoc = {
.num_bcms = ARRAY_SIZE(hscnoc_bcms),
};
+static const struct qcom_icc_desc mahua_hscnoc = {
+ .config = &glymur_hscnoc_regmap_config,
+ .nodes = mahua_hscnoc_nodes,
+ .num_nodes = ARRAY_SIZE(mahua_hscnoc_nodes),
+ .bcms = hscnoc_bcms,
+ .num_bcms = ARRAY_SIZE(hscnoc_bcms),
+};
+
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
[MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
[SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
@@ -2388,6 +2480,16 @@ static struct qcom_icc_node * const pcie_west_anoc_nodes[] = {
[SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC] = &srvc_pcie_west_aggre_noc,
};
+static struct qcom_icc_node * const mahua_pcie_west_anoc_nodes[] = {
+ [MASTER_PCIE_WEST_ANOC_CFG] = &qsm_pcie_west_anoc_cfg,
+ [MASTER_PCIE_2] = &xm_pcie_2,
+ [MASTER_PCIE_3B] = &xm_pcie_3b,
+ [MASTER_PCIE_4] = &xm_pcie_4,
+ [MASTER_PCIE_6] = &xm_pcie_6,
+ [SLAVE_PCIE_WEST_MEM_NOC] = &qns_pcie_west_mem_noc,
+ [SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC] = &srvc_pcie_west_aggre_noc,
+};
+
static const struct regmap_config glymur_pcie_west_anoc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -2405,6 +2507,15 @@ static const struct qcom_icc_desc glymur_pcie_west_anoc = {
.qos_requires_clocks = true,
};
+static const struct qcom_icc_desc mahua_pcie_west_anoc = {
+ .config = &glymur_pcie_west_anoc_regmap_config,
+ .nodes = mahua_pcie_west_anoc_nodes,
+ .num_nodes = ARRAY_SIZE(mahua_pcie_west_anoc_nodes),
+ .bcms = pcie_west_anoc_bcms,
+ .num_bcms = ARRAY_SIZE(pcie_west_anoc_bcms),
+ .qos_requires_clocks = true,
+};
+
static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] = {
&bcm_sn6,
};
@@ -2421,6 +2532,17 @@ static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] = {
[SLAVE_PCIE_6] = &xs_pcie_6,
};
+static struct qcom_icc_node * const mahua_pcie_west_slv_noc_nodes[] = {
+ [MASTER_HSCNOC_PCIE_WEST] = &qnm_hscnoc_pcie_west,
+ [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] = &qsm_cnoc_pcie_west_slave_cfg,
+ [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] = &qhs_hscnoc_pcie_west_ms_mpu_cfg,
+ [SLAVE_SERVICE_PCIE_WEST] = &srvc_pcie_west,
+ [SLAVE_PCIE_2] = &xs_pcie_2,
+ [SLAVE_PCIE_3B] = &xs_pcie_3b,
+ [SLAVE_PCIE_4] = &xs_pcie_4,
+ [SLAVE_PCIE_6] = &xs_pcie_6,
+};
+
static const struct regmap_config glymur_pcie_west_slv_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -2437,6 +2559,14 @@ static const struct qcom_icc_desc glymur_pcie_west_slv_noc = {
.num_bcms = ARRAY_SIZE(pcie_west_slv_noc_bcms),
};
+static const struct qcom_icc_desc mahua_pcie_west_slv_noc = {
+ .config = &glymur_pcie_west_slv_noc_regmap_config,
+ .nodes = mahua_pcie_west_slv_noc_nodes,
+ .num_nodes = ARRAY_SIZE(mahua_pcie_west_slv_noc_nodes),
+ .bcms = pcie_west_slv_noc_bcms,
+ .num_bcms = ARRAY_SIZE(pcie_west_slv_noc_bcms),
+};
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
&bcm_sn0,
&bcm_sn1,
@@ -2470,6 +2600,22 @@ static const struct qcom_icc_desc glymur_system_noc = {
.num_bcms = ARRAY_SIZE(system_noc_bcms),
};
+static int glymur_qnoc_probe(struct platform_device *pdev)
+{
+ if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
+ llcc_mc.channels = 8;
+ ebi.channels = 8;
+ } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
+ qns_llcc.channels = 8;
+ chm_apps.channels = 4;
+ qnm_pcie_west.buswidth = 32;
+ } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
+ qns_pcie_west_mem_noc.buswidth = 32;
+ }
+
+ return qcom_icc_rpmh_probe(pdev);
+}
+
static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc},
{ .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc},
@@ -2477,12 +2623,15 @@ static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc},
{ .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt},
{ .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg},
+ { .compatible = "qcom,mahua-cnoc-cfg", .data = &mahua_cnoc_cfg},
{ .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main},
{ .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc},
+ { .compatible = "qcom,mahua-hscnoc", .data = &mahua_hscnoc},
{ .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc},
{ .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc},
{ .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc},
{ .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt},
+ { .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt},
{ .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc},
{ .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc},
{ .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc},
@@ -2490,14 +2639,16 @@ static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc},
{ .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc},
{ .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
+ { .compatible = "qcom,mahua-pcie-west-anoc", .data = &mahua_pcie_west_anoc},
{ .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
+ { .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &mahua_pcie_west_slv_noc},
{ .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc},
{ }
};
MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
- .probe = qcom_icc_rpmh_probe,
+ .probe = glymur_qnoc_probe,
.remove = qcom_icc_rpmh_remove,
.driver = {
.name = "qnoc-glymur",
--
2.43.0On Fri, Jan 23, 2026 at 05:12:36PM +0000, Raviteja Laggyshetty wrote:
> Mahua is a derivative of the Glymur SoC. This patch extends the
Documentation/process/submitting-patches.rst, look for 'This patch'.
> Glymur driver to support Mahua by:
>
> 1. Adding new node definitions for interconnects that differ from Glymur
> (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
> 2. Reusing existing Glymur definitions for identical NoCs.
> 3. Overriding the channel and buswidth, with Mahua specific values for
> the differing NoCs
>
> Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> ---
> drivers/interconnect/qcom/glymur.c | 153 ++++++++++++++++++++++++++++++++++++-
> 1 file changed, 152 insertions(+), 1 deletion(-)
>
> +static struct qcom_icc_node * const mahua_cnoc_cfg_nodes[] = {
As you are patching other instances, why can't we just patch out the
PCI_3A out of these structures?
>
> +static int glymur_qnoc_probe(struct platform_device *pdev)
> +{
> + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
> + llcc_mc.channels = 8;
> + ebi.channels = 8;
> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
> + qns_llcc.channels = 8;
> + chm_apps.channels = 4;
> + qnm_pcie_west.buswidth = 32;
> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
> + qns_pcie_west_mem_noc.buswidth = 32;
> + }
Right here, set the node entries to NULL.
> +
> + return qcom_icc_rpmh_probe(pdev);
> +}
> +
> static const struct of_device_id qnoc_of_match[] = {
> { .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc},
> { .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc},
> @@ -2477,12 +2623,15 @@ static const struct of_device_id qnoc_of_match[] = {
> { .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc},
> { .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt},
> { .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg},
> + { .compatible = "qcom,mahua-cnoc-cfg", .data = &mahua_cnoc_cfg},
> { .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main},
> { .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc},
> + { .compatible = "qcom,mahua-hscnoc", .data = &mahua_hscnoc},
> { .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc},
> { .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc},
> { .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc},
> { .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt},
> + { .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt},
> { .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc},
> { .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc},
> { .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc},
> @@ -2490,14 +2639,16 @@ static const struct of_device_id qnoc_of_match[] = {
> { .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc},
> { .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc},
> { .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
> + { .compatible = "qcom,mahua-pcie-west-anoc", .data = &mahua_pcie_west_anoc},
> { .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
> + { .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &mahua_pcie_west_slv_noc},
> { .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc},
> { }
> };
> MODULE_DEVICE_TABLE(of, qnoc_of_match);
>
> static struct platform_driver qnoc_driver = {
> - .probe = qcom_icc_rpmh_probe,
> + .probe = glymur_qnoc_probe,
> .remove = qcom_icc_rpmh_remove,
> .driver = {
> .name = "qnoc-glymur",
>
> --
> 2.43.0
>
--
With best wishes
Dmitry
On 1/23/2026 11:28 PM, Dmitry Baryshkov wrote:
> On Fri, Jan 23, 2026 at 05:12:36PM +0000, Raviteja Laggyshetty wrote:
>> Mahua is a derivative of the Glymur SoC. This patch extends the
>
> Documentation/process/submitting-patches.rst, look for 'This patch'.
Will update the commit text, in next patch revision.
>
>> Glymur driver to support Mahua by:
>>
>> 1. Adding new node definitions for interconnects that differ from Glymur
>> (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
>> 2. Reusing existing Glymur definitions for identical NoCs.
>> 3. Overriding the channel and buswidth, with Mahua specific values for
>> the differing NoCs
>>
>> Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
>> ---
>> drivers/interconnect/qcom/glymur.c | 153 ++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 152 insertions(+), 1 deletion(-)
>>
>> +static struct qcom_icc_node * const mahua_cnoc_cfg_nodes[] = {
>
> As you are patching other instances, why can't we just patch out the
> PCI_3A out of these structures?
>
>>
>> +static int glymur_qnoc_probe(struct platform_device *pdev)
>> +{
>> + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
>> + llcc_mc.channels = 8;
>> + ebi.channels = 8;
>> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
>> + qns_llcc.channels = 8;
>> + chm_apps.channels = 4;
>> + qnm_pcie_west.buswidth = 32;
>> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
>> + qns_pcie_west_mem_noc.buswidth = 32;
>> + }
>
> Right here, set the node entries to NULL.
cnoc_cfg_nodes is declared as an array of const pointers, so the pointer
values cannot be reassigned after initialization. To change the addresses,
the const qualifier would need to be dropped. To preserve const, the
entire array has been duplicated instead by dropping the PCIE_3A related
nodes.
>
>> +
>> + return qcom_icc_rpmh_probe(pdev);
>> +}
>> +
>> static const struct of_device_id qnoc_of_match[] = {
>> { .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc},
>> { .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc},
>> @@ -2477,12 +2623,15 @@ static const struct of_device_id qnoc_of_match[] = {
>> { .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc},
>> { .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt},
>> { .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg},
>> + { .compatible = "qcom,mahua-cnoc-cfg", .data = &mahua_cnoc_cfg},
>> { .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main},
>> { .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc},
>> + { .compatible = "qcom,mahua-hscnoc", .data = &mahua_hscnoc},
>> { .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc},
>> { .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc},
>> { .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc},
>> { .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt},
>> + { .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt},
>> { .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc},
>> { .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc},
>> { .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc},
>> @@ -2490,14 +2639,16 @@ static const struct of_device_id qnoc_of_match[] = {
>> { .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc},
>> { .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc},
>> { .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
>> + { .compatible = "qcom,mahua-pcie-west-anoc", .data = &mahua_pcie_west_anoc},
>> { .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
>> + { .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &mahua_pcie_west_slv_noc},
>> { .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc},
>> { }
>> };
>> MODULE_DEVICE_TABLE(of, qnoc_of_match);
>>
>> static struct platform_driver qnoc_driver = {
>> - .probe = qcom_icc_rpmh_probe,
>> + .probe = glymur_qnoc_probe,
>> .remove = qcom_icc_rpmh_remove,
>> .driver = {
>> .name = "qnoc-glymur",
>>
>> --
>> 2.43.0
>>
>
On Mon, Jan 26, 2026 at 06:40:13PM +0530, Raviteja Laggyshetty wrote:
> On 1/23/2026 11:28 PM, Dmitry Baryshkov wrote:
> > On Fri, Jan 23, 2026 at 05:12:36PM +0000, Raviteja Laggyshetty wrote:
> >> +static int glymur_qnoc_probe(struct platform_device *pdev)
> >> +{
> >> + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
> >> + llcc_mc.channels = 8;
> >> + ebi.channels = 8;
> >> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
> >> + qns_llcc.channels = 8;
> >> + chm_apps.channels = 4;
> >> + qnm_pcie_west.buswidth = 32;
> >> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
> >> + qns_pcie_west_mem_noc.buswidth = 32;
> >> + }
> >
> > Right here, set the node entries to NULL.
>
> cnoc_cfg_nodes is declared as an array of const pointers, so the pointer
> values cannot be reassigned after initialization. To change the addresses,
> the const qualifier would need to be dropped. To preserve const, the
> entire array has been duplicated instead by dropping the PCIE_3A related
> nodes.
Why? Just drop the const instead of creating unnecessary (almost)
duplication.
> >
> >> +
--
With best wishes
Dmitry
On 1/26/2026 7:04 PM, Dmitry Baryshkov wrote:
> On Mon, Jan 26, 2026 at 06:40:13PM +0530, Raviteja Laggyshetty wrote:
>> On 1/23/2026 11:28 PM, Dmitry Baryshkov wrote:
>>> On Fri, Jan 23, 2026 at 05:12:36PM +0000, Raviteja Laggyshetty wrote:
>>>> +static int glymur_qnoc_probe(struct platform_device *pdev)
>>>> +{
>>>> + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
>>>> + llcc_mc.channels = 8;
>>>> + ebi.channels = 8;
>>>> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
>>>> + qns_llcc.channels = 8;
>>>> + chm_apps.channels = 4;
>>>> + qnm_pcie_west.buswidth = 32;
>>>> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
>>>> + qns_pcie_west_mem_noc.buswidth = 32;
>>>> + }
>>>
>>> Right here, set the node entries to NULL.
>>
>> cnoc_cfg_nodes is declared as an array of const pointers, so the pointer
>> values cannot be reassigned after initialization. To change the addresses,
>> the const qualifier would need to be dropped. To preserve const, the
>> entire array has been duplicated instead by dropping the PCIE_3A related
>> nodes.
>
> Why? Just drop the const instead of creating unnecessary (almost)
> duplication.
>
ok, Thanks for the suggestion Dmitry, will post the next revision by
addressing the comments.
>>>
>>>> +
>
On 1/23/26 6:58 PM, Dmitry Baryshkov wrote:
> On Fri, Jan 23, 2026 at 05:12:36PM +0000, Raviteja Laggyshetty wrote:
>> Mahua is a derivative of the Glymur SoC. This patch extends the
>
> Documentation/process/submitting-patches.rst, look for 'This patch'.
>
>> Glymur driver to support Mahua by:
>>
>> 1. Adding new node definitions for interconnects that differ from Glymur
>> (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
>> 2. Reusing existing Glymur definitions for identical NoCs.
>> 3. Overriding the channel and buswidth, with Mahua specific values for
>> the differing NoCs
>>
>> Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
>> ---
>> drivers/interconnect/qcom/glymur.c | 153 ++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 152 insertions(+), 1 deletion(-)
>>
>> +static struct qcom_icc_node * const mahua_cnoc_cfg_nodes[] = {
>
> As you are patching other instances, why can't we just patch out the
> PCI_3A out of these structures?
>
>>
>> +static int glymur_qnoc_probe(struct platform_device *pdev)
>> +{
>> + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
>> + llcc_mc.channels = 8;
>> + ebi.channels = 8;
>> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
>> + qns_llcc.channels = 8;
>> + chm_apps.channels = 4;
>> + qnm_pcie_west.buswidth = 32;
>> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
>> + qns_pcie_west_mem_noc.buswidth = 32;
>> + }
>
> Right here, set the node entries to NULL.
+1
Konrad
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