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Fri, 23 Jan 2026 09:13:13 -0800 (PST) Received: from [169.254.0.6] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3536ef9ddb9sm1191358a91.3.2026.01.23.09.13.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 09:13:12 -0800 (PST) From: Raviteja Laggyshetty Date: Fri, 23 Jan 2026 17:12:36 +0000 Subject: [PATCH 2/2] interconnect: qcom: glymur: Add Mahua SoC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-mahua_icc-v1-2-bc82cb087f1e@oss.qualcomm.com> References: <20260123-mahua_icc-v1-0-bc82cb087f1e@oss.qualcomm.com> In-Reply-To: <20260123-mahua_icc-v1-0-bc82cb087f1e@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Raviteja Laggyshetty Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Odelu Kukatla X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=eLUeTXp1 c=1 sm=1 tr=0 ts=6973ac2b cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=kREcFzCeUyQouyS3LoIA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: Y97aOQMFsaFaG7NUoxgIpxH_clO3y6g6 X-Proofpoint-ORIG-GUID: Y97aOQMFsaFaG7NUoxgIpxH_clO3y6g6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIzMDEyOSBTYWx0ZWRfX7kYnn/1+b2zx sUn0tY0NBUDHtAOxo4owaQ/GdWhFaJw4ZY0MmQE+iqpugkX8jS9WGcO631ElaW0kTUOvTJEhNVE psqAsDfvLTNN7TyRg5hbrHJRTLLJjmzq39H5QFqR7DiOTm3LzdztnZgSCXyHybqJroEZm4827F4 vUFsmKeDwVCQWtlmdbRtzbeBb4f+h7iqZHaA4YhWOdGX01at7H7C6K1iTvfPd8LVaxcS/IqmlTZ /kgl5tvdH/rsFR3RFH/cw1Gx1eCHiZx5EvF9TLwAoOUhTw9RFUvtJqaAq1DqO520J3zS7cpVn4V Qqe+5OtIkU3MJ27VPKu8z7YvJmys27RvYaJ8+cUbpGQTRAYcjoy5SDmfz+CrTNmIajN0e3yVPVs u9cxeUSDbYeO+7wuZcL0KeCJGtnPu1v2CEtU21TJO2w0ROJndnQESHFgZqvumV9doWUw5oC3Ozy mTAm4nGd7dylj0xpSbg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-23_02,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601230129 Mahua is a derivative of the Glymur SoC. This patch extends the Glymur driver to support Mahua by: 1. Adding new node definitions for interconnects that differ from Glymur (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC). 2. Reusing existing Glymur definitions for identical NoCs. 3. Overriding the channel and buswidth, with Mahua specific values for the differing NoCs Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/glymur.c | 153 +++++++++++++++++++++++++++++++++= +++- 1 file changed, 152 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom= /glymur.c index e5c07795a6c67ab8a59daf2fc4b8a5fa6dd014d6..65b03b2d5cdc69df0d54e209aed= 9c8e90309f577 100644 --- a/drivers/interconnect/qcom/glymur.c +++ b/drivers/interconnect/qcom/glymur.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include "bcm-voter.h" @@ -2040,6 +2041,60 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[]= =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; =20 +static struct qcom_icc_node * const mahua_cnoc_cfg_nodes[] =3D { + [MASTER_CNOC_CFG] =3D &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] =3D &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] =3D &qhs_ahb2phy1, + [SLAVE_AHB2PHY_2] =3D &qhs_ahb2phy2, + [SLAVE_AHB2PHY_3] =3D &qhs_ahb2phy3, + [SLAVE_AV1_ENC_CFG] =3D &qhs_av1_enc_cfg, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_DISPLAY_CFG] =3D &qhs_display_cfg, + [SLAVE_GFX3D_CFG] =3D &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] =3D &qhs_pcie1_cfg, + [SLAVE_PCIE_2_CFG] =3D &qhs_pcie2_cfg, + [SLAVE_PCIE_3B_CFG] =3D &qhs_pcie3b_cfg, + [SLAVE_PCIE_4_CFG] =3D &qhs_pcie4_cfg, + [SLAVE_PCIE_5_CFG] =3D &qhs_pcie5_cfg, + [SLAVE_PCIE_6_CFG] =3D &qhs_pcie6_cfg, + [SLAVE_PCIE_RSCC] =3D &qhs_pcie_rscc, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QSPI_0] =3D &qhs_qspi, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_QUP_1] =3D &qhs_qup1, + [SLAVE_QUP_2] =3D &qhs_qup2, + [SLAVE_SDCC_2] =3D &qhs_sdc2, + [SLAVE_SDCC_4] =3D &qhs_sdc4, + [SLAVE_SMMUV3_CFG] =3D &qhs_smmuv3_cfg, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] =3D &qhs_ufs_mem_cfg, + [SLAVE_USB2] =3D &qhs_usb2_0_cfg, + [SLAVE_USB3_0] =3D &qhs_usb3_0_cfg, + [SLAVE_USB3_1] =3D &qhs_usb3_1_cfg, + [SLAVE_USB3_2] =3D &qhs_usb3_2_cfg, + [SLAVE_USB3_MP] =3D &qhs_usb3_mp_cfg, + [SLAVE_USB4_0] =3D &qhs_usb4_0_cfg, + [SLAVE_USB4_1] =3D &qhs_usb4_1_cfg, + [SLAVE_USB4_2] =3D &qhs_usb4_2_cfg, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_CNOC_PCIE_SLAVE_EAST_CFG] =3D &qss_cnoc_pcie_slave_east_cfg, + [SLAVE_CNOC_PCIE_SLAVE_WEST_CFG] =3D &qss_cnoc_pcie_slave_west_cfg, + [SLAVE_LPASS_QTB_CFG] =3D &qss_lpass_qtb_cfg, + [SLAVE_CNOC_MNOC_CFG] =3D &qss_mnoc_cfg, + [SLAVE_NSP_QTB_CFG] =3D &qss_nsp_qtb_cfg, + [SLAVE_PCIE_EAST_ANOC_CFG] =3D &qss_pcie_east_anoc_cfg, + [SLAVE_PCIE_WEST_ANOC_CFG] =3D &qss_pcie_west_anoc_cfg, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + static const struct regmap_config glymur_cnoc_cfg_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -2056,6 +2111,14 @@ static const struct qcom_icc_desc glymur_cnoc_cfg = =3D { .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), }; =20 +static const struct qcom_icc_desc mahua_cnoc_cfg =3D { + .config =3D &glymur_cnoc_cfg_regmap_config, + .nodes =3D mahua_cnoc_cfg_nodes, + .num_nodes =3D ARRAY_SIZE(mahua_cnoc_cfg_nodes), + .bcms =3D cnoc_cfg_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), +}; + static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { &bcm_cn0, }; @@ -2115,6 +2178,27 @@ static struct qcom_icc_node * const hscnoc_nodes[] = =3D { [SLAVE_PCIE_WEST] =3D &qns_pcie_west, }; =20 +static struct qcom_icc_node * const mahua_hscnoc_nodes[] =3D { + [MASTER_GPU_TCU] =3D &alm_gpu_tcu, + [MASTER_PCIE_TCU] =3D &alm_pcie_qtc, + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_APPSS_PROC] =3D &chm_apps, + [MASTER_AGGRE_NOC_EAST] =3D &qnm_aggre_noc_east, + [MASTER_GFX3D] =3D &qnm_gpu, + [MASTER_LPASS_GEM_NOC] =3D &qnm_lpass, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] =3D &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] =3D &qnm_nsp_noc, + [MASTER_PCIE_EAST] =3D &qnm_pcie_east, + [MASTER_PCIE_WEST] =3D &qnm_pcie_west, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_GIC] =3D &xm_gic, + [SLAVE_HSCNOC_CNOC] =3D &qns_hscnoc_cnoc, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_PCIE_EAST] =3D &qns_pcie_east, + [SLAVE_PCIE_WEST] =3D &qns_pcie_west, +}; + static const struct regmap_config glymur_hscnoc_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -2131,6 +2215,14 @@ static const struct qcom_icc_desc glymur_hscnoc =3D { .num_bcms =3D ARRAY_SIZE(hscnoc_bcms), }; =20 +static const struct qcom_icc_desc mahua_hscnoc =3D { + .config =3D &glymur_hscnoc_regmap_config, + .nodes =3D mahua_hscnoc_nodes, + .num_nodes =3D ARRAY_SIZE(mahua_hscnoc_nodes), + .bcms =3D hscnoc_bcms, + .num_bcms =3D ARRAY_SIZE(hscnoc_bcms), +}; + static struct qcom_icc_node * const lpass_ag_noc_nodes[] =3D { [MASTER_LPIAON_NOC] =3D &qnm_lpiaon_noc, [SLAVE_LPASS_GEM_NOC] =3D &qns_lpass_ag_noc_gemnoc, @@ -2388,6 +2480,16 @@ static struct qcom_icc_node * const pcie_west_anoc_n= odes[] =3D { [SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC] =3D &srvc_pcie_west_aggre_noc, }; =20 +static struct qcom_icc_node * const mahua_pcie_west_anoc_nodes[] =3D { + [MASTER_PCIE_WEST_ANOC_CFG] =3D &qsm_pcie_west_anoc_cfg, + [MASTER_PCIE_2] =3D &xm_pcie_2, + [MASTER_PCIE_3B] =3D &xm_pcie_3b, + [MASTER_PCIE_4] =3D &xm_pcie_4, + [MASTER_PCIE_6] =3D &xm_pcie_6, + [SLAVE_PCIE_WEST_MEM_NOC] =3D &qns_pcie_west_mem_noc, + [SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC] =3D &srvc_pcie_west_aggre_noc, +}; + static const struct regmap_config glymur_pcie_west_anoc_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -2405,6 +2507,15 @@ static const struct qcom_icc_desc glymur_pcie_west_a= noc =3D { .qos_requires_clocks =3D true, }; =20 +static const struct qcom_icc_desc mahua_pcie_west_anoc =3D { + .config =3D &glymur_pcie_west_anoc_regmap_config, + .nodes =3D mahua_pcie_west_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(mahua_pcie_west_anoc_nodes), + .bcms =3D pcie_west_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_west_anoc_bcms), + .qos_requires_clocks =3D true, +}; + static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] =3D { &bcm_sn6, }; @@ -2421,6 +2532,17 @@ static struct qcom_icc_node * const pcie_west_slv_no= c_nodes[] =3D { [SLAVE_PCIE_6] =3D &xs_pcie_6, }; =20 +static struct qcom_icc_node * const mahua_pcie_west_slv_noc_nodes[] =3D { + [MASTER_HSCNOC_PCIE_WEST] =3D &qnm_hscnoc_pcie_west, + [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] =3D &qsm_cnoc_pcie_west_slave_cfg, + [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] =3D &qhs_hscnoc_pcie_west_ms_mpu_cfg, + [SLAVE_SERVICE_PCIE_WEST] =3D &srvc_pcie_west, + [SLAVE_PCIE_2] =3D &xs_pcie_2, + [SLAVE_PCIE_3B] =3D &xs_pcie_3b, + [SLAVE_PCIE_4] =3D &xs_pcie_4, + [SLAVE_PCIE_6] =3D &xs_pcie_6, +}; + static const struct regmap_config glymur_pcie_west_slv_noc_regmap_config = =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -2437,6 +2559,14 @@ static const struct qcom_icc_desc glymur_pcie_west_s= lv_noc =3D { .num_bcms =3D ARRAY_SIZE(pcie_west_slv_noc_bcms), }; =20 +static const struct qcom_icc_desc mahua_pcie_west_slv_noc =3D { + .config =3D &glymur_pcie_west_slv_noc_regmap_config, + .nodes =3D mahua_pcie_west_slv_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mahua_pcie_west_slv_noc_nodes), + .bcms =3D pcie_west_slv_noc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_west_slv_noc_bcms), +}; + static struct qcom_icc_bcm * const system_noc_bcms[] =3D { &bcm_sn0, &bcm_sn1, @@ -2470,6 +2600,22 @@ static const struct qcom_icc_desc glymur_system_noc = =3D { .num_bcms =3D ARRAY_SIZE(system_noc_bcms), }; =20 +static int glymur_qnoc_probe(struct platform_device *pdev) +{ + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) { + llcc_mc.channels =3D 8; + ebi.channels =3D 8; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) { + qns_llcc.channels =3D 8; + chm_apps.channels =3D 4; + qnm_pcie_west.buswidth =3D 32; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc"))= { + qns_pcie_west_mem_noc.buswidth =3D 32; + } + + return qcom_icc_rpmh_probe(pdev); +} + static const struct of_device_id qnoc_of_match[] =3D { { .compatible =3D "qcom,glymur-aggre1-noc", .data =3D &glymur_aggre1_noc}, { .compatible =3D "qcom,glymur-aggre2-noc", .data =3D &glymur_aggre2_noc}, @@ -2477,12 +2623,15 @@ static const struct of_device_id qnoc_of_match[] = =3D { { .compatible =3D "qcom,glymur-aggre4-noc", .data =3D &glymur_aggre4_noc}, { .compatible =3D "qcom,glymur-clk-virt", .data =3D &glymur_clk_virt}, { .compatible =3D "qcom,glymur-cnoc-cfg", .data =3D &glymur_cnoc_cfg}, + { .compatible =3D "qcom,mahua-cnoc-cfg", .data =3D &mahua_cnoc_cfg}, { .compatible =3D "qcom,glymur-cnoc-main", .data =3D &glymur_cnoc_main}, { .compatible =3D "qcom,glymur-hscnoc", .data =3D &glymur_hscnoc}, + { .compatible =3D "qcom,mahua-hscnoc", .data =3D &mahua_hscnoc}, { .compatible =3D "qcom,glymur-lpass-ag-noc", .data =3D &glymur_lpass_ag_= noc}, { .compatible =3D "qcom,glymur-lpass-lpiaon-noc", .data =3D &glymur_lpass= _lpiaon_noc}, { .compatible =3D "qcom,glymur-lpass-lpicx-noc", .data =3D &glymur_lpass_= lpicx_noc}, { .compatible =3D "qcom,glymur-mc-virt", .data =3D &glymur_mc_virt}, + { .compatible =3D "qcom,mahua-mc-virt", .data =3D &glymur_mc_virt}, { .compatible =3D "qcom,glymur-mmss-noc", .data =3D &glymur_mmss_noc}, { .compatible =3D "qcom,glymur-nsinoc", .data =3D &glymur_nsinoc}, { .compatible =3D "qcom,glymur-nsp-noc", .data =3D &glymur_nsp_noc}, @@ -2490,14 +2639,16 @@ static const struct of_device_id qnoc_of_match[] = =3D { { .compatible =3D "qcom,glymur-pcie-east-anoc", .data =3D &glymur_pcie_ea= st_anoc}, { .compatible =3D "qcom,glymur-pcie-east-slv-noc", .data =3D &glymur_pcie= _east_slv_noc}, { .compatible =3D "qcom,glymur-pcie-west-anoc", .data =3D &glymur_pcie_we= st_anoc}, + { .compatible =3D "qcom,mahua-pcie-west-anoc", .data =3D &mahua_pcie_west= _anoc}, { .compatible =3D "qcom,glymur-pcie-west-slv-noc", .data =3D &glymur_pcie= _west_slv_noc}, + { .compatible =3D "qcom,mahua-pcie-west-slv-noc", .data =3D &mahua_pcie_w= est_slv_noc}, { .compatible =3D "qcom,glymur-system-noc", .data =3D &glymur_system_noc}, { } }; MODULE_DEVICE_TABLE(of, qnoc_of_match); =20 static struct platform_driver qnoc_driver =3D { - .probe =3D qcom_icc_rpmh_probe, + .probe =3D glymur_qnoc_probe, .remove =3D qcom_icc_rpmh_remove, .driver =3D { .name =3D "qnoc-glymur", --=20 2.43.0