From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
set them to allow using Multi-IRQ mode when supported.
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
.../devicetree/bindings/net/nxp,s32-dwmac.yaml | 42 +++++++++++++++++++---
1 file changed, 37 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
index 2b8b74c5feec..31d1dfeb098e 100644
--- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright 2021-2024 NXP
+# Copyright 2021-2026 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
@@ -33,10 +33,22 @@ properties:
- description: GMAC PHY mode control register
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 11
interrupt-names:
- const: macirq
+ items:
+ - const: macirq
+ - const: tx-queue-0
+ - const: rx-queue-0
+ - const: tx-queue-1
+ - const: rx-queue-1
+ - const: tx-queue-2
+ - const: rx-queue-2
+ - const: tx-queue-3
+ - const: rx-queue-3
+ - const: tx-queue-4
+ - const: rx-queue-4
clocks:
items:
@@ -75,8 +87,28 @@ examples:
reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 0: tx, rx */
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 1: tx, rx */
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 2: tx, rx */
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 3: tx, rx */
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 4: tx, rx */
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0", "rx-queue-0",
+ "tx-queue-1", "rx-queue-1",
+ "tx-queue-2", "rx-queue-2",
+ "tx-queue-3", "rx-queue-3",
+ "tx-queue-4", "rx-queue-4";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
--
2.47.0On Fri, Jan 23, 2026 at 11:09:55AM +0100, Jan Petrous via B4 Relay wrote:
> From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
>
> The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
> set them to allow using Multi-IRQ mode when supported.
The binding only supports s32{g,r} devices, why is the existing minimum
retained? What devices are going to not have all 11 interrupts
connected?
Cheers,
Conor.
>
> Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
> ---
> .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 42 +++++++++++++++++++---
> 1 file changed, 37 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> index 2b8b74c5feec..31d1dfeb098e 100644
> --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> -# Copyright 2021-2024 NXP
> +# Copyright 2021-2026 NXP
> %YAML 1.2
> ---
> $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
> @@ -33,10 +33,22 @@ properties:
> - description: GMAC PHY mode control register
>
> interrupts:
> - maxItems: 1
> + minItems: 1
> + maxItems: 11
>
> interrupt-names:
> - const: macirq
> + items:
> + - const: macirq
> + - const: tx-queue-0
> + - const: rx-queue-0
> + - const: tx-queue-1
> + - const: rx-queue-1
> + - const: tx-queue-2
> + - const: rx-queue-2
> + - const: tx-queue-3
> + - const: rx-queue-3
> + - const: tx-queue-4
> + - const: rx-queue-4
>
> clocks:
> items:
> @@ -75,8 +87,28 @@ examples:
> reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
> <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
> interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "macirq";
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 0: tx, rx */
> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 1: tx, rx */
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 2: tx, rx */
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 3: tx, rx */
> + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 4: tx, rx */
> + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq",
> + "tx-queue-0", "rx-queue-0",
> + "tx-queue-1", "rx-queue-1",
> + "tx-queue-2", "rx-queue-2",
> + "tx-queue-3", "rx-queue-3",
> + "tx-queue-4", "rx-queue-4";
> snps,mtl-rx-config = <&mtl_rx_setup>;
> snps,mtl-tx-config = <&mtl_tx_setup>;
> clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
>
> --
> 2.47.0
>
>
On Fri, Jan 23, 2026 at 05:13:03PM +0000, Conor Dooley wrote:
> On Fri, Jan 23, 2026 at 11:09:55AM +0100, Jan Petrous via B4 Relay wrote:
> > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
> >
> > The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
> > set them to allow using Multi-IRQ mode when supported.
>
> The binding only supports s32{g,r} devices, why is the existing minimum
> retained? What devices are going to not have all 11 interrupts
> connected?
>
The original idea was to support backward compatibility, as older DTs
didn't contain queue-based interrupt lines described.
But now, when you asked, I started to think it is not needed,
the requirement for backward compatibility is managed inside the driver
and yaml shall describe the hardware not used configuration.
Is it my understanding right? Should I provide v4 with minimum = 11?
BR.
/Jan
On Mon, Jan 26, 2026 at 01:46:45PM +0100, Jan Petrous wrote:
> On Fri, Jan 23, 2026 at 05:13:03PM +0000, Conor Dooley wrote:
> > On Fri, Jan 23, 2026 at 11:09:55AM +0100, Jan Petrous via B4 Relay wrote:
> > > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
> > >
> > > The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
> > > set them to allow using Multi-IRQ mode when supported.
> >
> > The binding only supports s32{g,r} devices, why is the existing minimum
> > retained? What devices are going to not have all 11 interrupts
> > connected?
> >
>
> The original idea was to support backward compatibility, as older DTs
> didn't contain queue-based interrupt lines described.
>
> But now, when you asked, I started to think it is not needed,
> the requirement for backward compatibility is managed inside the driver
> and yaml shall describe the hardware not used configuration.
Just to be clear, cos the last portion of that "yaml shall..." isn't to
me, you mean that the driver will support 1 or 11 interrupts but you
will make the binding only allow 11? That would be fine.
Just note in the commit message that all of these devices have the 11
interrupts.
> Is it my understanding right? Should I provide v4 with minimum = 11?
On Mon, Jan 26, 2026 at 08:00:33PM +0000, Conor Dooley wrote:
> On Mon, Jan 26, 2026 at 01:46:45PM +0100, Jan Petrous wrote:
> > On Fri, Jan 23, 2026 at 05:13:03PM +0000, Conor Dooley wrote:
> > > On Fri, Jan 23, 2026 at 11:09:55AM +0100, Jan Petrous via B4 Relay wrote:
> > > > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
> > > >
> > > > The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
> > > > set them to allow using Multi-IRQ mode when supported.
> > >
> > > The binding only supports s32{g,r} devices, why is the existing minimum
> > > retained? What devices are going to not have all 11 interrupts
> > > connected?
> > >
> >
> > The original idea was to support backward compatibility, as older DTs
> > didn't contain queue-based interrupt lines described.
> >
> > But now, when you asked, I started to think it is not needed,
> > the requirement for backward compatibility is managed inside the driver
> > and yaml shall describe the hardware not used configuration.
>
> Just to be clear, cos the last portion of that "yaml shall..." isn't to
> me, you mean that the driver will support 1 or 11 interrupts but you
> will make the binding only allow 11? That would be fine.
> Just note in the commit message that all of these devices have the 11
> interrupts.
>
Well, all those supported devices have 11 interrupts connected (1x MAC),
then 5x RX (queue0..queue4) and 5x TX (queue0..queue4).
Until now, the driver was using on MAC IRQ, so the only one shared line.
Now, we are enabling support for per-queue interrupts, what means for
supported SoCs up to 11 IRQs as the DWMAC IP on S32G/R has 5 queues.
The driver can still opearate on this one shared IRQ mode, but
if the DT node configuration describes all IRQs, then the driver switch
to multi-IRQ mode. What allows better distribution of processor core
load.
So the 11 IRQs are the maximum value, in the case when all queues are
used. But I can imagine some other use-cases, when not all queues
are enabled, ie. only queue0 and quque1. In that case, the driver will
use some subset of all IRQs.
That means that DT can contain only lesser interrupt list then maximum.
I feel like having "minItems: 1" shall cover such use-case.
BR.
/Jan
On Tue, Jan 27, 2026 at 01:51:58PM +0100, Jan Petrous wrote:
> On Mon, Jan 26, 2026 at 08:00:33PM +0000, Conor Dooley wrote:
> > On Mon, Jan 26, 2026 at 01:46:45PM +0100, Jan Petrous wrote:
> > > On Fri, Jan 23, 2026 at 05:13:03PM +0000, Conor Dooley wrote:
> > > > On Fri, Jan 23, 2026 at 11:09:55AM +0100, Jan Petrous via B4 Relay wrote:
> > > > > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
> > > > >
> > > > > The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
> > > > > set them to allow using Multi-IRQ mode when supported.
> > > >
> > > > The binding only supports s32{g,r} devices, why is the existing minimum
> > > > retained? What devices are going to not have all 11 interrupts
> > > > connected?
> > > >
> > >
> > > The original idea was to support backward compatibility, as older DTs
> > > didn't contain queue-based interrupt lines described.
> > >
> > > But now, when you asked, I started to think it is not needed,
> > > the requirement for backward compatibility is managed inside the driver
> > > and yaml shall describe the hardware not used configuration.
> >
> > Just to be clear, cos the last portion of that "yaml shall..." isn't to
> > me, you mean that the driver will support 1 or 11 interrupts but you
> > will make the binding only allow 11? That would be fine.
> > Just note in the commit message that all of these devices have the 11
> > interrupts.
> >
>
> Well, all those supported devices have 11 interrupts connected (1x MAC),
> then 5x RX (queue0..queue4) and 5x TX (queue0..queue4).
>
> Until now, the driver was using on MAC IRQ, so the only one shared line.
> Now, we are enabling support for per-queue interrupts, what means for
> supported SoCs up to 11 IRQs as the DWMAC IP on S32G/R has 5 queues.
>
> The driver can still opearate on this one shared IRQ mode, but
> if the DT node configuration describes all IRQs, then the driver switch
> to multi-IRQ mode. What allows better distribution of processor core
> load.
> So the 11 IRQs are the maximum value, in the case when all queues are
> used. But I can imagine some other use-cases, when not all queues
> are enabled, ie. only queue0 and quque1. In that case, the driver will
Since all of the devices have 11 interrupts, this would be software
configuration and the devicetree should contain all 11 even if shared
mode is desired, to reflect how the hardware is configured. I think
minItems should be changed to 11, unless another device gets added later
that does not have all 11 connected.
> use some subset of all IRQs.
> That means that DT can contain only lesser interrupt list then maximum.
>
> I feel like having "minItems: 1" shall cover such use-case.
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