From nobody Tue Feb 10 01:31:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A07E437BE76; Fri, 23 Jan 2026 10:10:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163008; cv=none; b=tW1JNz52t8wdomKfv4aisZPGsOn1isq4avh37n8Wr31vbz7Qg409/3naMIRHnshpAkvuTC6RS5HhPg5v6BuG2iiSPpdvEXsxE+Vdn6WFRnEzn19Ty8YQMruLfLzGzAvZBhgV1uVj6XyfKiAiPLcwMq5fraOjXff590WyOmPy9pQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163008; c=relaxed/simple; bh=/sAomtMqIiV4lWIWGav839h/zFzdTQirNdkOR5mNhU0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QVYRNj4L+JgnSPYwWh9suUKlaJhtRQ+Yhu6g5mYOtBMxznyrcAkrSb/hWeS2euBEi+sWHanh6vN9Zr+QanZDjwQ89lI42tsVhE8LQ9SBBN+xj2Vy4BW7SEMYoGuAkzASpFOoAjSjazLZcwviMp71vXdvgxIle6K/VavuMSczoUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fyhP8r3Z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fyhP8r3Z" Received: by smtp.kernel.org (Postfix) with ESMTPS id 416D2C19422; Fri, 23 Jan 2026 10:10:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769163008; bh=/sAomtMqIiV4lWIWGav839h/zFzdTQirNdkOR5mNhU0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=fyhP8r3ZXRrOygHw67HEbOfFrYr7wWWZ33H1k8HOZJryMJuDch4T8temjkk5GYmC7 9tQjG93bTEMnxLIX/ht2tTnXiocUObiU2liyb0k9mFVD/BhXVDi2GrsCJeIg6zKxm0 CI8gKz6FvqZ4I4+3deULJrj6O88Fg4XpsRZO84uW8lKuGI2imi8kN471wSIB+MVf8n TNKvExpmxg5vqFpx63SWjc94jx9exZIipf2MNRDb/78Qfml60uRZUCztDciIh1Il5I B5i+78VhSFNmduFyFaHhKXq9H1vhOU/0dCMitzFM8wH5aEJnpetIwWwgKMtLGM57SM iI6UuMOUlMTmQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32040D7236A; Fri, 23 Jan 2026 10:10:08 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Fri, 23 Jan 2026 11:09:55 +0100 Subject: [PATCH v3 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-dwmac_multi_irq-v3-2-cc53f2be8961@oss.nxp.com> References: <20260123-dwmac_multi_irq-v3-0-cc53f2be8961@oss.nxp.com> In-Reply-To: <20260123-dwmac_multi_irq-v3-0-cc53f2be8961@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769163006; l=3065; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=QlhAxzb6ufWFEeVPNUgM7miu/hiQulE6Q8b8EApJlOk=; b=OW/N7V1HzGLYrGTMeffBI/HGQ18ys4ES2yPHazroIv1gnwyf9JRv+gEL7NA03PioA7+PoHsTa PkFniBERZY5D/FcV4Av9/tuTz5HjUFghDQKkw2aw6wRJwduwYjVNzSI X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines, set them to allow using Multi-IRQ mode when supported. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 42 ++++++++++++++++++= +--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 2b8b74c5feec..31d1dfeb098e 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2021-2024 NXP +# Copyright 2021-2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# @@ -33,10 +33,22 @@ properties: - description: GMAC PHY mode control register =20 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 11 =20 interrupt-names: - const: macirq + items: + - const: macirq + - const: tx-queue-0 + - const: rx-queue-0 + - const: tx-queue-1 + - const: rx-queue-1 + - const: tx-queue-2 + - const: rx-queue-2 + - const: tx-queue-3 + - const: rx-queue-3 + - const: tx-queue-4 + - const: rx-queue-4 =20 clocks: items: @@ -75,8 +87,28 @@ examples: reg =3D <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; clocks =3D <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; --=20 2.47.0