Introduce Top Level Mode Multiplexer support for Mahua, a 12-core
variant of Qualcomm's Glymur compute SoC.
Mahua shares the same pin configuration and GPIO layout as Glymur
but requires different PDC (Power Domain Controller) wake IRQ
mappings for proper wake-up functionality.
Changes:
- Add DeviceTree bindings for Mahua SoC TLMM block
- Add Mahua-specific GPIO to PDC IRQ mappings
- Add mahua tlmm soc data
- Enable probe time config selection based on the compatible string
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
---
Changes in v3:
- dt-bindings: updated commit message based on review feedback
- pinctrl: updated commit message based on review feedback
- pinctrl: Fix spacing to use single newline between structures
- Link to v2: https://lore.kernel.org/r/20260105-pinctrl-qcom-mahua-tlmm-v2-0-7ac036f700de@oss.qualcomm.com
Changes in v2:
- dt-bindings: updated commit message based on review feedback
- pinctrl: drop GPIO 155 from the PDC wakeirq map
- Link to v1: https://lore.kernel.org/r/20260102-pinctrl-qcom-mahua-tlmm-v1-0-0edd71af08b2@oss.qualcomm.com
---
Gopikrishna Garmidi (2):
dt-bindings: pinctrl: qcom,glymur-tlmm: Document Mahua TLMM block
pinctrl: qcom: glymur: Add Mahua TLMM support
.../bindings/pinctrl/qcom,glymur-tlmm.yaml | 6 ++-
drivers/pinctrl/qcom/pinctrl-glymur.c | 46 ++++++++++++++++++++--
2 files changed, 47 insertions(+), 5 deletions(-)
---
base-commit: cc3aa43b44bdb43dfbac0fcb51c56594a11338a8
change-id: 20260102-pinctrl-qcom-mahua-tlmm-433644bae64c
Best regards,
--
Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>