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The PDC wake IRQ map differs since PDC handles the interrupt for GPIO 155 instead of GPIO 143 as seen on Glymur. Signed-off-by: Gopikrishna Garmidi Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yam= l b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml index d2b0cfeffb50..2836a1a10579 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml @@ -10,14 +10,16 @@ maintainers: - Bjorn Andersson =20 description: - Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC. + Top Level Mode Multiplexer pin controller in Qualcomm Glymur and Mahua S= oC. =20 allOf: - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# =20 properties: compatible: - const: qcom,glymur-tlmm + enum: + - qcom,glymur-tlmm + - qcom,mahua-tlmm =20 reg: maxItems: 1 --=20 2.34.1 From nobody Mon Feb 9 10:49:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8D0C3ECBE3 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1244af22aaasm18714842c88.17.2026.01.20.09.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jan 2026 09:23:44 -0800 (PST) From: Gopikrishna Garmidi Date: Tue, 20 Jan 2026 09:22:51 -0800 Subject: [PATCH v3 2/2] pinctrl: qcom: glymur: Add Mahua TLMM support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260120-pinctrl-qcom-mahua-tlmm-v3-2-8809a09dc628@oss.qualcomm.com> References: <20260120-pinctrl-qcom-mahua-tlmm-v3-0-8809a09dc628@oss.qualcomm.com> In-Reply-To: <20260120-pinctrl-qcom-mahua-tlmm-v3-0-8809a09dc628@oss.qualcomm.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Pankaj Patil , Sibi Sankar Cc: Bjorn Andersson , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gopikrishna Garmidi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768929822; l=3365; i=gopikrishna.garmidi@oss.qualcomm.com; s=20260102; h=from:subject:message-id; bh=xOKCUEK79jZEMU0XsZlL2vcpGR/Zktrh+jM8ZBiVhRI=; b=qrUCFFOijYpi0NRnPuwotZ0+mtkgYDX/J8Ma/yrxiniHFiTgZMsI1/oUcU41BuL7lMC4DE6KH f+SgnrQfjL6DaMdS6weSdiIui5skgoxLGS3/3cj7yVMUYU0Jeue7mvl X-Developer-Key: i=gopikrishna.garmidi@oss.qualcomm.com; a=ed25519; pk=TkSjNEhrfsj90i3wkABTZtAjLNr2cfYsujaTvyOIDsE= X-Proofpoint-GUID: rsH58mJte520BXCQknxJ7b7NLbVSn9ZW X-Authority-Analysis: v=2.4 cv=Q43fIo2a c=1 sm=1 tr=0 ts=696fba21 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=p1T0IFexb8msloUdZnoA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-ORIG-GUID: rsH58mJte520BXCQknxJ7b7NLbVSn9ZW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIwMDE0NSBTYWx0ZWRfX3aQxWI5CTWTw W1DXoUrnY3aGwtMm9Fpbwa2fH8yLrgOOjChEQszhpB8sDaEmx9UKPJoBO5H/MB67ZCJCUJtRDTz Q/QLJSVhkOQlOymKVBYUxfFXxtTZ2qL7TCTmcYqcgJTXOHYZxAtlaTx9DmNz7DL6MwotmM/wLm2 19+M0P/SLa7O7ntpYCFW2buRkWkxy/AUFxCgMAUYWb3twIi6bgxeEGKbifAd2SzekDIb8duoT7J LqFkHTiBfY+1R8Nr+3leqJPSBkNaB0VZuhzAUG7HT3LYaz2ebcfloMF3yzdN52sREi1+stDVGqn SV4cr5uHu9GxP+u9AU7nse42vnb+j1EZ27IUvxwKbi+ZXvoAhtzy8Fi/bQB4bET3qo63+O35YqX l3vVDfZs2MvAyyCymbBSPwHZ6MYBtovZq/hrPiYUHaJEYAQTAKiDqxIUjh91pqL1o5UlhiXQnwp pbYYSDFph9PPFru1J6Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-20_04,2026-01-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601200145 Mahua TLMM block is identical to Glymur, but the PDC wake IRQ map differs since PDC handles the interrupt for GPIO 155 instead of GPIO 143 as seen on Glymur. Hence add the Mahua-specific PDC map to the Glymur TLMM driver. Signed-off-by: Gopikrishna Garmidi Reviewed-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/pinctrl-glymur.c | 46 +++++++++++++++++++++++++++++++= +--- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/p= inctrl-glymur.c index 335005084b6b..44f9745325b7 100644 --- a/drivers/pinctrl/qcom/pinctrl-glymur.c +++ b/drivers/pinctrl/qcom/pinctrl-glymur.c @@ -1729,6 +1729,26 @@ static const struct msm_gpio_wakeirq_map glymur_pdc_= map[] =3D { { 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 }, }; =20 +static const struct msm_gpio_wakeirq_map mahua_pdc_map[] =3D { + { 0, 116 }, { 2, 114 }, { 3, 115 }, { 4, 175 }, { 5, 176 }, + { 7, 111 }, { 11, 129 }, { 13, 130 }, { 15, 112 }, { 19, 113 }, + { 23, 187 }, { 27, 188 }, { 28, 121 }, { 29, 122 }, { 30, 136 }, + { 31, 203 }, { 32, 189 }, { 34, 174 }, { 35, 190 }, { 36, 191 }, + { 39, 124 }, { 43, 192 }, { 47, 193 }, { 51, 123 }, { 53, 133 }, + { 55, 125 }, { 59, 131 }, { 64, 134 }, { 65, 150 }, { 66, 186 }, + { 67, 132 }, { 68, 195 }, { 71, 135 }, { 75, 196 }, { 79, 197 }, + { 83, 198 }, { 84, 181 }, { 85, 199 }, { 87, 200 }, { 91, 201 }, + { 92, 182 }, { 93, 183 }, { 94, 184 }, { 95, 185 }, { 98, 202 }, + { 105, 157 }, { 113, 128 }, { 121, 117 }, { 123, 118 }, { 125, 119 }, + { 129, 120 }, { 131, 126 }, { 132, 160 }, { 133, 194 }, { 134, 127 }, + { 141, 137 }, { 144, 138 }, { 145, 139 }, { 147, 140 }, { 148, 141 }, + { 150, 146 }, { 151, 147 }, { 153, 148 }, { 154, 144 }, { 155, 159 }, + { 156, 149 }, { 157, 151 }, { 163, 142 }, { 172, 143 }, { 181, 145 }, + { 193, 161 }, { 196, 152 }, { 203, 177 }, { 208, 178 }, { 215, 162 }, + { 217, 153 }, { 220, 154 }, { 221, 155 }, { 228, 179 }, { 230, 180 }, + { 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 }, +}; + static const struct msm_pinctrl_soc_data glymur_tlmm =3D { .pins =3D glymur_pins, .npins =3D ARRAY_SIZE(glymur_pins), @@ -1742,14 +1762,34 @@ static const struct msm_pinctrl_soc_data glymur_tlm= m =3D { .egpio_func =3D 11, }; =20 +static const struct msm_pinctrl_soc_data mahua_tlmm =3D { + .pins =3D glymur_pins, + .npins =3D ARRAY_SIZE(glymur_pins), + .functions =3D glymur_functions, + .nfunctions =3D ARRAY_SIZE(glymur_functions), + .groups =3D glymur_groups, + .ngroups =3D ARRAY_SIZE(glymur_groups), + .ngpios =3D 251, + .wakeirq_map =3D mahua_pdc_map, + .nwakeirq_map =3D ARRAY_SIZE(mahua_pdc_map), + .egpio_func =3D 11, +}; + static const struct of_device_id glymur_tlmm_of_match[] =3D { - { .compatible =3D "qcom,glymur-tlmm", }, - { } + { .compatible =3D "qcom,glymur-tlmm", .data =3D &glymur_tlmm }, + { .compatible =3D "qcom,mahua-tlmm", .data =3D &mahua_tlmm }, + { }, }; =20 static int glymur_tlmm_probe(struct platform_device *pdev) { - return msm_pinctrl_probe(pdev, &glymur_tlmm); + const struct msm_pinctrl_soc_data *data; + + data =3D of_device_get_match_data(&pdev->dev); + if (!data) + return -ENODEV; + + return msm_pinctrl_probe(pdev, data); } =20 static struct platform_driver glymur_tlmm_driver =3D { --=20 2.34.1