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[PATCH 4/4] drm/msm/dpu: fix SSPP_UBWC_STATIC_CTRL programming on UBWC 5.x+

Dmitry Baryshkov posted 4 patches 3 weeks, 2 days ago
There is a newer version of this series
[PATCH 4/4] drm/msm/dpu: fix SSPP_UBWC_STATIC_CTRL programming on UBWC 5.x+
Posted by Dmitry Baryshkov 3 weeks, 2 days ago 
Code in dpu_hw_sspp_setup_format() doesn't handle UBWC versions bigger
than 4.0. Replace switch-case with if-else checks, making sure that the
register is initialized on UBWC 5.x (and later) hosts.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 41 ++++++++++++++---------------
 1 file changed, 20 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index a99e33230514..b0c97f5e47ea 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -279,6 +279,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
 
 	if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
 		u32 hbb = ctx->ubwc->highest_bank_bit - 13;
+		u32 ctrl_val;
 
 		if (MSM_FORMAT_IS_UBWC(fmt))
 			opmode |= MDSS_MDP_OP_BWC_EN;
@@ -286,30 +287,28 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
 		DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
 			DPU_FETCH_CONFIG_RESET_VALUE |
 			hbb << 18);
-		switch (ctx->ubwc->ubwc_enc_version) {
-		case UBWC_1_0:
+
+		if (ctx->ubwc->ubwc_enc_version == UBWC_1_0) {
 			fast_clear = fmt->alpha_enable ? BIT(31) : 0;
-			DPU_REG_WRITE(c, ubwc_static_ctrl_off,
-					fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
-					BIT(8) |
-					(hbb << 4));
-			break;
-		case UBWC_2_0:
+			ctrl_val = fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
+				BIT(8) | (hbb << 4);
+		} else if (ctx->ubwc->ubwc_enc_version == UBWC_2_0) {
 			fast_clear = fmt->alpha_enable ? BIT(31) : 0;
-			DPU_REG_WRITE(c, ubwc_static_ctrl_off,
-					fast_clear | (ctx->ubwc->ubwc_swizzle) |
-					(hbb << 4));
-			break;
-		case UBWC_3_0:
-			DPU_REG_WRITE(c, ubwc_static_ctrl_off,
-					BIT(30) | (ctx->ubwc->ubwc_swizzle) |
-					(hbb << 4));
-			break;
-		case UBWC_4_0:
-			DPU_REG_WRITE(c, ubwc_static_ctrl_off,
-					MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
-			break;
+			ctrl_val = fast_clear | ctx->ubwc->ubwc_swizzle | (hbb << 4);
+		} else if (ctx->ubwc->ubwc_enc_version == UBWC_3_0) {
+			ctrl_val = BIT(30) | (ctx->ubwc->ubwc_swizzle) | (hbb << 4);
+		} else if (ctx->ubwc->ubwc_enc_version == UBWC_4_0) {
+			ctrl_val = MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30);
+		} else { /* UBWC 5.0+ */
+			if (MSM_FORMAT_IS_YUV(fmt))
+				ctrl_val = 0;
+			else if (MSM_FORMAT_IS_DX(fmt)) /* or FP16, but it's unsupported */
+				ctrl_val = BIT(30);
+			else
+				ctrl_val = BIT(30) | BIT(31);
 		}
+
+		DPU_REG_WRITE(c, ubwc_static_ctrl_off, ctrl_val);
 	}
 
 	opmode |= MDSS_MDP_OP_PE_OVERRIDE;

-- 
2.47.3
Re: [PATCH 4/4] drm/msm/dpu: fix SSPP_UBWC_STATIC_CTRL programming on UBWC 5.x+
Posted by Rob Clark 3 weeks ago 
On Fri, Jan 16, 2026 at 10:36 PM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> Code in dpu_hw_sspp_setup_format() doesn't handle UBWC versions bigger
> than 4.0. Replace switch-case with if-else checks, making sure that the
> register is initialized on UBWC 5.x (and later) hosts.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 41 ++++++++++++++---------------
>  1 file changed, 20 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index a99e33230514..b0c97f5e47ea 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -279,6 +279,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
>
>         if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
>                 u32 hbb = ctx->ubwc->highest_bank_bit - 13;
> +               u32 ctrl_val;
>
>                 if (MSM_FORMAT_IS_UBWC(fmt))
>                         opmode |= MDSS_MDP_OP_BWC_EN;
> @@ -286,30 +287,28 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
>                 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
>                         DPU_FETCH_CONFIG_RESET_VALUE |
>                         hbb << 18);
> -               switch (ctx->ubwc->ubwc_enc_version) {
> -               case UBWC_1_0:
> +
> +               if (ctx->ubwc->ubwc_enc_version == UBWC_1_0) {
>                         fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> -                       DPU_REG_WRITE(c, ubwc_static_ctrl_off,
> -                                       fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> -                                       BIT(8) |
> -                                       (hbb << 4));
> -                       break;
> -               case UBWC_2_0:
> +                       ctrl_val = fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> +                               BIT(8) | (hbb << 4);
> +               } else if (ctx->ubwc->ubwc_enc_version == UBWC_2_0) {
>                         fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> -                       DPU_REG_WRITE(c, ubwc_static_ctrl_off,
> -                                       fast_clear | (ctx->ubwc->ubwc_swizzle) |
> -                                       (hbb << 4));
> -                       break;
> -               case UBWC_3_0:
> -                       DPU_REG_WRITE(c, ubwc_static_ctrl_off,
> -                                       BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> -                                       (hbb << 4));
> -                       break;
> -               case UBWC_4_0:
> -                       DPU_REG_WRITE(c, ubwc_static_ctrl_off,
> -                                       MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> -                       break;
> +                       ctrl_val = fast_clear | ctx->ubwc->ubwc_swizzle | (hbb << 4);
> +               } else if (ctx->ubwc->ubwc_enc_version == UBWC_3_0) {
> +                       ctrl_val = BIT(30) | (ctx->ubwc->ubwc_swizzle) | (hbb << 4);
> +               } else if (ctx->ubwc->ubwc_enc_version == UBWC_4_0) {
> +                       ctrl_val = MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30);
> +               } else { /* UBWC 5.0+ */

Is this the same for UBWC 6?  Should we warn on version > UBWC_6_0?

BR,
-R

> +                       if (MSM_FORMAT_IS_YUV(fmt))
> +                               ctrl_val = 0;
> +                       else if (MSM_FORMAT_IS_DX(fmt)) /* or FP16, but it's unsupported */
> +                               ctrl_val = BIT(30);
> +                       else
> +                               ctrl_val = BIT(30) | BIT(31);
>                 }
> +
> +               DPU_REG_WRITE(c, ubwc_static_ctrl_off, ctrl_val);
>         }
>
>         opmode |= MDSS_MDP_OP_PE_OVERRIDE;
>
> --
> 2.47.3
>

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