Hello,

This series adds support for the QSPI controller available on Renesas
RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last
SPI patch for details).

Adding support for this SoC required a few adaptations in the Cadence
QSPI driver. The bulk of the work is in the few last patches. Everything
else is just misc style fixes and improvements which bothered me while I
was wandering.

In order to support all constraints, I sometimes used a new quirk (for
the write protection feature and the "no indirect mode"), and sometimes
used the compatible directly. The ones I thought might not be RZ/N1
specific have been implemented under the form of a quirk, in order to
ease their reuse. The other adaptations, which I believe are more
Renesas specific, have been handled using the compatible. This is all
very arbitrary, and can be discussed.

Thanks,
Miquèl

Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
---
Changes in v2:
- Fix commit log of DT binding patch, following Krzysztof's comment.
- Fix properties order in DTSI.
- Rebase on top of spi/for-next and fix all conflicts.
- Simplify even further the code in the cleanup patches following
  Pratyush's advices.
- Link to v1: https://lore.kernel.org/r/20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com

---
Miquel Raynal (1):
      spi: cadence-qspi: Make sure we filter out unsupported ops

Miquel Raynal (Schneider Electric) (12):
      spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list
      spi: cadence-qspi: Align definitions
      spi: cadence-qspi: Fix style and improve readability
      spi: cadence-qspi: Fix ORing style and alignments
      spi: cadence-qspi: Remove an useless operation
      spi: cadence-qspi: Fix probe error path and remove
      spi: cadence-qspi: Try hard to disable the clocks
      spi: cadence-qspi: Kill cqspi_jh7110_clk_init
      spi: cadence-qspi: Add a flag for controllers without indirect access support
      spi: cadence-qspi: Make sure write protection is disabled
      spi: cadence-qspi: Add support for the Renesas RZ/N1 controller
      ARM: dts: r9a06g032: Describe the QSPI controller

 .../devicetree/bindings/spi/cdns,qspi-nor.yaml     |   4 +
 arch/arm/boot/dts/renesas/r9a06g032.dtsi           |  14 ++
 drivers/spi/spi-cadence-quadspi.c                  | 260 ++++++++++-----------
 3 files changed, 144 insertions(+), 134 deletions(-)
---
base-commit: 0afb3ab76ffb521700af678ea931d31192f93260
change-id: 20251219-schneider-6-19-rc1-qspi-7c3e1547af6d

Best regards,
-- 
Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>

On Thu, Jan 15, 2026 at 10:24:51AM +0100, Miquel Raynal (Schneider Electric) wrote:

> This series adds support for the QSPI controller available on Renesas
> RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last
> SPI patch for details).

I can access the SPI-NOR on the Renesas Eval board
(r9a06g032-rzn1d400-db.dts) just fine with it. So, for all patches:

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

I'll send the board DTS addition as RFC in a minute.

Hello Miquel,

On 15/01/26 14:54, Miquel Raynal (Schneider Electric) wrote:
> Hello,
> 
> This series adds support for the QSPI controller available on Renesas
> RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last
> SPI patch for details).
> 
> Adding support for this SoC required a few adaptations in the Cadence
> QSPI driver. The bulk of the work is in the few last patches. Everything
> else is just misc style fixes and improvements which bothered me while I
> was wandering.
> 
> In order to support all constraints, I sometimes used a new quirk (for
> the write protection feature and the "no indirect mode"), and sometimes
> used the compatible directly. The ones I thought might not be RZ/N1
> specific have been implemented under the form of a quirk, in order to
> ease their reuse. The other adaptations, which I believe are more
> Renesas specific, have been handled using the compatible. This is all
> very arbitrary, and can be discussed.
> 
> Thanks,
> Miquèl
> 
> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>

Thank you for the series! Tested it on TI's AM62A SK with
OSPI NAND (Winbond's W35N01JW).

Controller fails to probe with the following message:

[    1.868863] cadence-qspi fc40000.spi: Cannot claim mandatory QSPI ref 
clock.

Regards,
Santhosh.

> ---
> Changes in v2:
> - Fix commit log of DT binding patch, following Krzysztof's comment.
> - Fix properties order in DTSI.
> - Rebase on top of spi/for-next and fix all conflicts.
> - Simplify even further the code in the cleanup patches following
>    Pratyush's advices.
> - Link to v1: https://lore.kernel.org/r/20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com
> 
> ---
> Miquel Raynal (1):
>        spi: cadence-qspi: Make sure we filter out unsupported ops
> 
> Miquel Raynal (Schneider Electric) (12):
>        spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list
>        spi: cadence-qspi: Align definitions
>        spi: cadence-qspi: Fix style and improve readability
>        spi: cadence-qspi: Fix ORing style and alignments
>        spi: cadence-qspi: Remove an useless operation
>        spi: cadence-qspi: Fix probe error path and remove
>        spi: cadence-qspi: Try hard to disable the clocks
>        spi: cadence-qspi: Kill cqspi_jh7110_clk_init
>        spi: cadence-qspi: Add a flag for controllers without indirect access support
>        spi: cadence-qspi: Make sure write protection is disabled
>        spi: cadence-qspi: Add support for the Renesas RZ/N1 controller
>        ARM: dts: r9a06g032: Describe the QSPI controller
> 
>   .../devicetree/bindings/spi/cdns,qspi-nor.yaml     |   4 +
>   arch/arm/boot/dts/renesas/r9a06g032.dtsi           |  14 ++
>   drivers/spi/spi-cadence-quadspi.c                  | 260 ++++++++++-----------
>   3 files changed, 144 insertions(+), 134 deletions(-)
> ---
> base-commit: 0afb3ab76ffb521700af678ea931d31192f93260
> change-id: 20251219-schneider-6-19-rc1-qspi-7c3e1547af6d
> 
> Best regards,

Hi Santhosh,

On 20/01/2026 at 14:52:38 +0530, Santhosh Kumar K <s-k6@ti.com> wrote:

> Hello Miquel,
>
> On 15/01/26 14:54, Miquel Raynal (Schneider Electric) wrote:
>> Hello,
>> This series adds support for the QSPI controller available on Renesas
>> RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last
>> SPI patch for details).
>> Adding support for this SoC required a few adaptations in the Cadence
>> QSPI driver. The bulk of the work is in the few last patches. Everything
>> else is just misc style fixes and improvements which bothered me while I
>> was wandering.
>> In order to support all constraints, I sometimes used a new quirk (for
>> the write protection feature and the "no indirect mode"), and sometimes
>> used the compatible directly. The ones I thought might not be RZ/N1
>> specific have been implemented under the form of a quirk, in order to
>> ease their reuse. The other adaptations, which I believe are more
>> Renesas specific, have been handled using the compatible. This is all
>> very arbitrary, and can be discussed.
>> Thanks,
>> Miquèl
>> Signed-off-by: Miquel Raynal (Schneider Electric)
>> <miquel.raynal@bootlin.com>
>
> Thank you for the series! Tested it on TI's AM62A SK with
> OSPI NAND (Winbond's W35N01JW).
>
> Controller fails to probe with the following message:
>
> [    1.868863] cadence-qspi fc40000.spi: Cannot claim mandatory QSPI ref
> clock.

Strange, I was nonetheless careful not to change the existing
behaviour on other SoCs. I have that board, I will give it a try.

Thanks a lot for the feedback.
Miquèl

Hello,

>> Thank you for the series! Tested it on TI's AM62A SK with
>> OSPI NAND (Winbond's W35N01JW).
>>
>> Controller fails to probe with the following message:
>>
>> [    1.868863] cadence-qspi fc40000.spi: Cannot claim mandatory QSPI ref
>> clock.
>
> Strange, I was nonetheless careful not to change the existing
> behaviour on other SoCs. I have that board, I will give it a try.

I made a mistake with the clk_bulk_* API data indeed. probe now succeeds
with both my custom board and the AM62a7 LP SK. v3 coming soon.

Thanks,
Miquèl