From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 363C635B139; Thu, 15 Jan 2026 09:25:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469142; cv=none; b=tHHcvYJNW2qvVLbGBbhua/MXsO3wY8y7TtPPNo+f3Vw4JPthEXeCr3VwIF66vMD5m9ulzz6ffP8Ab0uM/JRcd4IodiZxTiX3WXPehUkaQ4cnNAVlmOVzWyYUPFD8K/3zWaTiwP5arPZ9qaGsxo+fb0g0OosJp+/LJL54gKTh56Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469142; c=relaxed/simple; bh=p5NslQCxTSi9APH6Nu9G2/rRRMoxXVza/nVtRoQsCXI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Yw9MRXiPI30DkVMK64PoaOP0/34AByoxoZN9psNzllzMZTEIRFTxP8asF7ggj0VKAo/mAHop1PUg+zlSPp6jW52dXvgygghAFBg3gwiekZykZ14C5AF9NFwcEj1AM1tgIYxof255yAEuGHs1QZiBSqF+1mPMFjKanEBB3KfNNXQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=IXdRpb3h; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="IXdRpb3h" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id C8F12C1F1E6; Thu, 15 Jan 2026 09:25:07 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 8225D606B6; Thu, 15 Jan 2026 09:25:34 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7526310B6851D; Thu, 15 Jan 2026 10:25:31 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469133; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=OeTAsflrIMlCORoJPATDkdX8lDo51A/BHMo9XZjAk1U=; b=IXdRpb3hDLNw/03VPINe9l2q4kqECYaG2N/C/x/1CpylaEm+5AUGjZsPo9HlCRKGjk2vqj dZUublrHIKYvkisLzSGaCoxL5ldVWxAlkP4n+53I99MUxrCLv6+zr7yLHY4X3oW9cf0+S7 mRuJJsGA2EBhvNEFIcl6zD8n2iw8c9LoAyaYq+TxYfBepKaswBh4Si8VV3AuG44wz+qkVd E71dIG4+U0JCJiXVRLv58iYFWVUPm2pI5nkCNZcJ8TZuEhc/nrTmlXGQiIWIZQqzCA+eTc UdgYm0bMx5vtRZ9f4wNB+1RYxhB6CFaERpUlg+SI8S0lvrphD4hQbegUptXZgg== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:24:52 +0100 Subject: [PATCH v2 01/13] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-1-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add support for the Renesas RZ/N1D400 QSPI controller. This SoC is identified in the bindings with its other name: r9a06g032. It is part of the RZ/N1 family, which contains a "D" and a "S" variant. IPs in this SoC are typically described using 3 compatibles (the SoC specific compatible, the family compatible, and the original Cadence IP compatible), follow this convention. Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 53a52fb8b819..62948990defb 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -80,6 +80,10 @@ properties: # controllers are meant to be used with flashes of all kinds, # ie. also NAND flashes, not only NOR flashes. - const: cdns,qspi-nor + - items: + - const: renesas,r9a06g032-qspi + - const: renesas,rzn1-qspi + - const: cdns,qspi-nor - const: cdns,qspi-nor deprecated: true =20 --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0826735CB76; Thu, 15 Jan 2026 09:25:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469144; cv=none; b=MtqwGtpfn68FH3Q7PLiJKnfJn3l8XvZZLDlvYhUSyrsUbklcnFk0l42smPvsxFxayuUHWlxNtawUKNIinfReo1juzSZ/Mn6JcpE0YanrdcEK43m1srcDydVU5Z5Y0EdA/qhaeOCwxfjjwhiGsXBj0pS7fbd3852bMNtwdltPQSA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469144; c=relaxed/simple; bh=Ggvetuvct7MvQ9A8+EoRnZU4gklUA92KH90msuWi1vE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jchaJEplcQi9DGpJRNNzeSH0QaWyFnhg0fyolwDE7Rg35pudvsQYGnQOQyfl6QWmGXZcTQUvqL5OQuUU8TpLiNa69C6EdD4MlZMGQURDIyIpsezbciLnxo30fs2fZlpcSrZIcW7xi0Xw+k4iXPCyz3uDke4Yi6okVAHSckrBcXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=2n+2Eslo; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="2n+2Eslo" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id C600DC1F1E7; Thu, 15 Jan 2026 09:25:09 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 65AB9606B6; Thu, 15 Jan 2026 09:25:36 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9DD2910B684FE; Thu, 15 Jan 2026 10:25:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469135; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=T01uagbj2uK4jDe5pgcQoMBv7LdHax0xggZOac1szRs=; b=2n+2Eslor/wVtrqQZytvCXSG5jIZUgCfuPVSapJGmtLP9skvoag9T9rTBh9jS9IS1iRtsV 3AD8av2fmSEXH6bvS3C4FokHQg8SQH1ew6PmASQtJ3k2bE+c4q+4NBQ3iJqdEmx4CzbM3b x9gG5YuNfH0gnT+Kcr2Gab3omRl1CNvyuI8YoIxrZtRTx0LNXAwyjNI/pUpSDaxyXRpFv2 b4pkHfl+6agj/hdQP/TwTuCSq48/88naJkNS1y1gDHiWFeZaL66oZWyW1TQ+dbsLqgknUm sLTkCr+4I42WjHusFXwml0NrMl1RApoCeHgubtrfPtZTXUEFpTWaA3YOkuxurg== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:24:53 +0100 Subject: [PATCH v2 02/13] spi: cadence-qspi: Align definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-2-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Fix alignment on the #defines. Reviewed-by: Pratyush Yadav Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index b1cf182d6566..cc28da7fc686 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,7 +40,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_DISABLE_DAC_MODE BIT(1) #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) -#define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_SLOW_SRAM BIT(4) #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) #define CQSPI_RD_NO_IRQ BIT(6) #define CQSPI_DMA_SET_MASK BIT(7) --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAFBE35EDC7 for ; Thu, 15 Jan 2026 09:25:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469147; cv=none; b=mpGoywEoUq9fO0XIdF05xD4Kj5ObE0o4hSAx7++gEzNhGoZ5DtDLKhoWi4mPhyg/CtExid4AxdATwIigfIdlbJ221XDV/X3Nz1wBttnGH3sJXg4d8jxZ8TrSi8RuMwXYyhHN5jS4tqyPMmFFGiaIKBenCYuxklxUFMeET4DwzvA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469147; c=relaxed/simple; bh=r4xsrvUEkrisBm830uVOi5LF7CumvVgNOo2uu+EAufY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OT0jQgz4k7bIxx7Qwh7KBZQ2J3NJhJPY9guHI4tQqHy+1iRgnChLmJh2leBnyy2xnSd3owlLOovJLjhNee0XQYZ9xF/6+LYMurHjrWc498f6SvcpJaZvbGlJksA0TzaIgW7BEQNiZsMV17nJBlm3/g7Al75eKvKY3AWIdz5nr7g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=EbrZSyQK; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="EbrZSyQK" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id B30994E420FF; Thu, 15 Jan 2026 09:25:38 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 8913C606B6; Thu, 15 Jan 2026 09:25:38 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A922710B68530; Thu, 15 Jan 2026 10:25:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469137; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=gltgqZxplCK6T7f5+zOiN0+WD5c1Yq1xx9kIlIzwwZA=; b=EbrZSyQKJUUTB5NptiNKVCUwI7JbCfuXCDSqTCUozcFI3T5j2UrOTsmyVkgOEPo/n7zw8q Q6ovswpKZ3Q/l2UNgF/GaCeA6AS12yaf2EJ1crWjCzBRbJsSBbMa4RK5DIF8mVbzyAsOl1 9Nn3vzMCVqQfCSos34PzHlwObu62D8CULhpT3ji1ZL7oZG40ffCdknBVTmoRVeuwFMqvkp lnlYx2ctKUjO53L3IwfwUAsRFZmeemQoWYO0eLH+K/Krb877qTO2GNR1w8OqA2bSZTBXVp 3L2MRb1AjlD4JizkrcZBOay9/GPNsN436/Fi/k1d9KCx8kibaNede0IKmQiuRQ== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:24:54 +0100 Subject: [PATCH v2 03/13] spi: cadence-qspi: Fix style and improve readability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-3-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 It took me several seconds to correctly understand this block. I understand the goal: showing that we are in the if, or in one of the two other cases. Improve the organization of the code to both improve readability and fix the style. Suggested-by: Pratyush Yadav Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index cc28da7fc686..c0a507953c58 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -374,17 +374,12 @@ static irqreturn_t cqspi_irq_handler(int this_irq, vo= id *dev) /* Clear interrupt */ writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); =20 - if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { - if (ddata->get_dma_status(cqspi)) { - complete(&cqspi->transfer_complete); - return IRQ_HANDLED; - } - } - - else if (!cqspi->slow_sram) - irq_status &=3D CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; - else + if (cqspi->use_dma_read && ddata && ddata->get_dma_status) + irq_status =3D ddata->get_dma_status(cqspi); + else if (cqspi->slow_sram) irq_status &=3D CQSPI_IRQ_MASK_RD_SLOW_SRAM | CQSPI_IRQ_MASK_WR; + else + irq_status &=3D CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; =20 if (irq_status) complete(&cqspi->transfer_complete); --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EBAE261B78 for ; Thu, 15 Jan 2026 09:25:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469144; cv=none; b=D6TRW6QpZ7PW3IhJi1EGOQ+1uArR+JDsbjLnYeiiglrPJ+BHmcW6NB94Gs05eIu7HY9R/kzVfkBP/kTJwm0ufUuSvV6IjZjiCrzVDvNwIW9DffhRywzlEs4ZRct0h/V+69oMFe54D08hv7ESPg64KsuEAWd57ibDK20txh0Glg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469144; c=relaxed/simple; bh=gT3QETcdcCGbiRCmC0wzi2c4JfCVpnZFE7d7jQ8SPKk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Thu, 15 Jan 2026 09:25:40 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C703A10B6851D; Thu, 15 Jan 2026 10:25:37 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469139; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=fVq92moEtVi/BN63BXxUDdkiQFjKN+FXnZ7Ltkyl1bY=; b=LbF55K/K5uHSRSmLh1Xf7sG/MuyUWRMEEdAhxmSRF4z6BVVO7ifHJPgM7S20cqA851fPOM B2ezzNtOIX5N8eAZCLiuIO1vSYlFipB3LYYB5cax3BUmhQ5HdmhErmivVpw+P9SY6epFEH PVtUWA5VfUw395DakTn7aK6Gf49EpHkna3+8BrsyG52TTnUwLR98BzAGT15xd7M6PtbzK3 SkN5aHDS2TzzQx1P9xbE5+zqLmT737NzKLszUqVSPmcRVUph+8V7QN4Uzc33Ol48ezuWGz P6sKwuqfxO/yCmVaVibTwzX9EGQPXcAbAddx/yeITCFoudOsobF1RaEJOm12Vg== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:24:55 +0100 Subject: [PATCH v2 04/13] spi: cadence-qspi: Fix ORing style and alignments Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-4-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 These definitions do not follow the standard patterns. Alignments are incoherent and the logical OR symbols '|' are misplaced. Reorganize these definitions. There is no functional change. Acked-by: Pratyush Yadav Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index c0a507953c58..8eb80b4b76eb 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -2130,26 +2130,23 @@ static const struct cqspi_driver_platdata intel_lgm= _qspi =3D { }; =20 static const struct cqspi_driver_platdata socfpga_qspi =3D { - .quirks =3D CQSPI_DISABLE_DAC_MODE - | CQSPI_NO_SUPPORT_WR_COMPLETION - | CQSPI_SLOW_SRAM - | CQSPI_DISABLE_STIG_MODE - | CQSPI_DISABLE_RUNTIME_PM, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | + CQSPI_SLOW_SRAM | CQSPI_DISABLE_STIG_MODE | + CQSPI_DISABLE_RUNTIME_PM, }; =20 static const struct cqspi_driver_platdata versal_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, - .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA - | CQSPI_DMA_SET_MASK, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | + CQSPI_DMA_SET_MASK, .indirect_read_dma =3D cqspi_versal_indirect_read_dma, .get_dma_status =3D cqspi_get_versal_dma_status, }; =20 static const struct cqspi_driver_platdata versal2_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, - .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA - | CQSPI_DMA_SET_MASK - | CQSPI_SUPPORT_DEVICE_RESET, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | + CQSPI_DMA_SET_MASK | CQSPI_SUPPORT_DEVICE_RESET, .indirect_read_dma =3D cqspi_versal_indirect_read_dma, .get_dma_status =3D cqspi_get_versal_dma_status, }; @@ -2166,7 +2163,7 @@ static const struct cqspi_driver_platdata pensando_cd= ns_qspi =3D { static const struct cqspi_driver_platdata mobileye_eyeq5_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | - CQSPI_RD_NO_IRQ, + CQSPI_RD_NO_IRQ, }; =20 static const struct of_device_id cqspi_dt_ids[] =3D { --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A733435E52E; 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arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ZCNCGrtQ" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 9B162C1F1E5; Thu, 15 Jan 2026 09:25:16 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 542C3606B6; Thu, 15 Jan 2026 09:25:43 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DF8BB10B6852D; Thu, 15 Jan 2026 10:25:39 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469141; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=TfqfY/NbV/xcFiwyzhB5ld1l7j/zKWnZt4iHWq7aaQk=; b=ZCNCGrtQRoTJcAkbPkTeKXN0/Tdw8Dlg13VN+SIRLsJZEfxJ2U6UwuqwNwmBjMIrBdVT98 rH7KrgPMrGxCPgtO5QlYeAvQBTqxvWqjeq5rWj4KclZlr2oLxZwoM+Z8v2W/t4/vO9MtCx ycrPNmtL1qSt2Dmu86SlkQ6cbVP2aFmp92jazLaC7FyHi3wytjE8X6/dLVBbdEC67o/OoX Mp7sIPpNQXFa1ZAsSwANqdmHwKl0ZBm25HxuSRxkGY5PCM9DigbNp0k852axttgph2mh+z 9TBhT81PokT9QIq3Y+cwre6hD/s+cbp60tadlAYCSypEv9A3gOek+XHZLkAl1w== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:24:56 +0100 Subject: [PATCH v2 05/13] spi: cadence-qspi: Remove an useless operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-5-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Right above writing the register value back based on 'div' value, there is the following check: if (div > CQSPI_REG_CONFIG_BAUD_MASK) div =3D CQSPI_REG_CONFIG_BAUD_MASK; which means div does not need to be AND'ed against the bitfield mask. Remove this redundant operation. Reviewed-by: Pratyush Yadav Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 8eb80b4b76eb..06f6c5979229 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1258,7 +1258,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st= *cqspi) =20 reg =3D readl(reg_base + CQSPI_REG_CONFIG); reg &=3D ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); - reg |=3D (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; + reg |=3D div << CQSPI_REG_CONFIG_BAUD_LSB; writel(reg, reg_base + CQSPI_REG_CONFIG); } =20 --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6040B35F8A1; Thu, 15 Jan 2026 09:25:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469148; cv=none; b=Bhc8dUTp0a9pd8VjvhVbzd1ODr5WCqpSEAIPTb8dvU4aSPRIDQeEi7+Vc6JIb+MKPf8N09co9oNeSUgNK0U+7xGexHgqY6cC1/Z/cY1c6aKZIPOGpluLZio/UBNl7F3jh/F44IS+MOnId9iZsdNwAEQW7utnK8ofa7D/1yd49oU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469148; c=relaxed/simple; bh=igVog/TuQlFhP2II37PWCpQHbGnK/zT5ZUv8hPXJn2c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gHoVliTts/wH5xPc5J1i7aev7Mr5Y7GBQXbBls3xL55LSrfg2AYSdY0tqXNenp1xNqsq6Ej3cLLAs3H0QIYYhlQk1Zd6GE1ZzDR3s4BPnrUxyAZQFbrEJz8o2aB5Kpkj37POK4XwssArlUuB68u6lny/Y7WiKxcDHkvCdc2LDo0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=cJiHUmex; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="cJiHUmex" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 4837BC1F1E6; Thu, 15 Jan 2026 09:25:18 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 01301606B6; Thu, 15 Jan 2026 09:25:45 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 29FBE10B68454; Thu, 15 Jan 2026 10:25:42 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469143; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=0c7taA1Mf9rP/X5UWyC/94bk5u6l6JsrkY0WDU5uFtU=; b=cJiHUmexPQw4YbPrHTSm/5gJ5v9ZY6S2CHXXJuAkw5R3QfXpheYmStQ3zQaS1VN4rHTYHG NryXsHr1pX5cOpnOUKnxgqpBAlTtvFlPHCWo3s3HH/C4pi0pco8Rar4j7M3WaKRFyqnTow iPsVuU9J2MmAau5zBkCNh4v1+cpk2UM2NeQPgAKEbnreAi50uIzHp2KA54CWKsnzxgCqqT Z60p/S3G9R2ia9n3p2/3uBDm9pk5hPRolbQJFPIsuC7uW2MAD8jRwafZZk1j5+aascC7Ef vDzJkAVlJgijLoHz9C+2iVILptMDRD42vXke8KjfAGnpx3ERXibrQ3dlqo9nUw== From: Miquel Raynal Date: Thu, 15 Jan 2026 10:24:57 +0100 Subject: [PATCH v2 06/13] spi: cadence-qspi: Make sure we filter out unsupported ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-6-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The Cadence driver does not support anything else than repeating the command opcode twice while in octal DTR mode. Make this clear by checking for this in the ->supports_op() hook. Signed-off-by: Miquel Raynal Reviewed-by: Pratyush Yadav Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 06f6c5979229..fc9f6e8dd549 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1531,6 +1531,10 @@ static bool cqspi_supports_mem_op(struct spi_mem *me= m, return false; if (op->data.nbytes && op->data.buswidth !=3D 8) return false; + + /* A single opcode is supported, it will be repeated */ + if ((op->cmd.opcode >> 8) !=3D (op->cmd.opcode & 0xFF)) + return false; } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5357B35A958; Thu, 15 Jan 2026 09:25:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469150; cv=none; b=duV4sb4gSQJcd4nuMglR/o5aD2TwblzYy/SvRo13sftqMSP27N8bzsdmm1iH7OR8i26CLtD8lOtHdEXRxeRdn5c+qa916AzR4NAeyKDO3ecn0uj4cx9yS9LKu1Hf2YCw6en4lyIyU1PORCbdkIrih3xtsMX6dhVy22XnNyYBVGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469150; c=relaxed/simple; bh=4ChcxgJ20ygOMkquhdw/NryD2NYOxrCWlnz86m/NWRE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jTHq9Hl8eRarnykSRCqbzQkBtRnYT8/HSkqJqycmQREo1WH/fjWInkrFyVhYRwbe4gnfmyCcrmROItZT+fGdnlNrcL4DZ2q5tpgSuJgz501FFqvcSK0Qv0up+bHnbpQZ7+oCtTXcOYa+07Izp9sUgA8Jn/B41SjBGDGk3ox82Cg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=hXdYIown; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="hXdYIown" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id E62094E420F8; Thu, 15 Jan 2026 09:25:46 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id BBAA8606B6; Thu, 15 Jan 2026 09:25:46 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 162AC10B6851D; Thu, 15 Jan 2026 10:25:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469145; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=7V6Ua6NlB73Y1NHrQe6OIWoJuKOK58B8bTr6opLMKfM=; b=hXdYIownx1rVCUQwh0WOVqN9cSMQLyoq2hGlTZxaYdcGmDA+V666FSGiKTGGE+jwZUptSA Ha2QTnomWm/RCpe6++3WWx3XgQQG9oWkfAeCHOB2y/uQrqn5yrDAo2/ZgHuIqOUOOJqQYJ rUwNTcqrdq7Je20IXP74u5E1e5k34n2nSNq0eP1WCRrVbTIX2gGUUdEXOCzZ4gn/OGA6B1 wAO0qZBOiQ00/IetB3NCZ/pxNNoG/Bn/HRUjWlstH07DgBIwFVH9YABNfufKW/VOa6wSnw 75A+IrdQ3IQqHTEGwlql2VmcipA+gVb/dpdFDBg67uzv1CEbPpwUCVz1vI00Cw== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:24:58 +0100 Subject: [PATCH v2 07/13] spi: cadence-qspi: Fix probe error path and remove Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-7-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The probe has been modified by many different users, it is hard to track history, but for sure its current state is partially broken. One easy rule to follow is to drop/free/release the resources in the opposite order they have been queried. Fix the labels, the order for freeing the resources, and add the missing DMA channel step. Replicate these changes in the remove path as well. Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 44 ++++++++++++++++++++++-------------= ---- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index fc9f6e8dd549..4bfe65af458e 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1890,7 +1890,7 @@ static int cqspi_probe(struct platform_device *pdev) ret =3D clk_prepare_enable(cqspi->clk); if (ret) { dev_err(dev, "Cannot enable QSPI clock.\n"); - goto probe_clk_failed; + goto disable_rpm; } =20 /* Obtain QSPI reset control */ @@ -1898,14 +1898,14 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc)) { ret =3D PTR_ERR(rstc); dev_err(dev, "Cannot get QSPI reset.\n"); - goto probe_reset_failed; + goto disable_clk; } =20 rstc_ocp =3D devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); if (IS_ERR(rstc_ocp)) { ret =3D PTR_ERR(rstc_ocp); dev_err(dev, "Cannot get QSPI OCP reset.\n"); - goto probe_reset_failed; + goto disable_clk; } =20 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { @@ -1913,7 +1913,7 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc_ref)) { ret =3D PTR_ERR(rstc_ref); dev_err(dev, "Cannot get QSPI REF reset.\n"); - goto probe_reset_failed; + goto disable_clk; } reset_control_assert(rstc_ref); reset_control_deassert(rstc_ref); @@ -1955,7 +1955,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata->jh7110_clk_init) { ret =3D cqspi_jh7110_clk_init(pdev, cqspi); if (ret) - goto probe_reset_failed; + goto disable_clk; } if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) cqspi->disable_stig_mode =3D true; @@ -1963,7 +1963,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata->quirks & CQSPI_DMA_SET_MASK) { ret =3D dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); if (ret) - goto probe_reset_failed; + goto disable_clks; } } =20 @@ -1974,7 +1974,7 @@ static int cqspi_probe(struct platform_device *pdev) pdev->name, cqspi); if (ret) { dev_err(dev, "Cannot request IRQ.\n"); - goto probe_reset_failed; + goto disable_clks; } =20 cqspi_wait_idle(cqspi); @@ -2001,31 +2001,36 @@ static int cqspi_probe(struct platform_device *pdev) ret =3D cqspi_request_mmap_dma(cqspi); if (ret =3D=3D -EPROBE_DEFER) { dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n"); - goto probe_setup_failed; + goto disable_controller; } } =20 ret =3D spi_register_controller(host); if (ret) { dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); - goto probe_setup_failed; + goto release_dma_chan; } =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) pm_runtime_put_autosuspend(dev); =20 return 0; -probe_setup_failed: - if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - pm_runtime_disable(dev); + +release_dma_chan: + if (cqspi->rx_chan) + dma_release_channel(cqspi->rx_chan); +disable_controller: cqspi_controller_enable(cqspi, 0); -probe_reset_failed: +disable_clks: if (cqspi->is_jh7110) cqspi_jh7110_disable_clk(pdev, cqspi); - +disable_clk: if (pm_runtime_get_sync(&pdev->dev) >=3D 0) clk_disable_unprepare(cqspi->clk); -probe_clk_failed: +disable_rpm: + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) + pm_runtime_disable(dev); + return ret; } =20 @@ -2043,18 +2048,19 @@ static void cqspi_remove(struct platform_device *pd= ev) cqspi_wait_idle(cqspi); =20 spi_unregister_controller(cqspi->host); - cqspi_controller_enable(cqspi, 0); =20 if (cqspi->rx_chan) dma_release_channel(cqspi->rx_chan); =20 - if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - if (pm_runtime_get_sync(&pdev->dev) >=3D 0) - clk_disable(cqspi->clk); + cqspi_controller_enable(cqspi, 0); =20 if (cqspi->is_jh7110) cqspi_jh7110_disable_clk(pdev, cqspi); =20 + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) + if (pm_runtime_get_sync(&pdev->dev) >=3D 0) + clk_disable(cqspi->clk); + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07B4735CB75 for ; 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bh=vpyrsnWMYxiBaejIiwzp/rVmHvQvnlGjk2HnSaZLv1I=; b=l21yX7ot3xvF2RGZmeyKiVsXlVoTlONCWcqSLT+dQlbxkl6unVePe7GXK7rKqjMvzsZ4BL hb9HrUDrmJ/dFrE2xubZyXtOQkRW12gjHmMh0o2Cnr/g9cjs+CBhzXris/ic9G5LB9tNZj 7EnJ6O3pc8fnFKHz68sWwqdmIiuUB9OuwHAfxWJs6kpX38Sp7e2tmu4XbYT0650lokBxig 5NraivdIx8wv7Zq2BenzYcSHyAUWFvB4lQIxJal1GP7FQ0AqNLKM78TMyCExtFcFMiFtn0 CeM9EeYIWpWP6DmWtPUdop+eHY0HgzK5QeC7VkihVuK0jR2enoAoeVUsNvDQXw== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:24:59 +0100 Subject: [PATCH v2 08/13] spi: cadence-qspi: Try hard to disable the clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-8-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In the remove path, we should try hard to perform all steps as we simply cannot fail. The "no runtime PM" quirk must only alter the state of the RPM core, but the clocks should still be disabled if that is possible. Move the disable call outside of the RPM quirk. Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 4bfe65af458e..af0ad24d8d39 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -2039,6 +2039,7 @@ static void cqspi_remove(struct platform_device *pdev) const struct cqspi_driver_platdata *ddata; struct cqspi_st *cqspi =3D platform_get_drvdata(pdev); struct device *dev =3D &pdev->dev; + int ret =3D 0; =20 ddata =3D of_device_get_match_data(dev); =20 @@ -2058,8 +2059,10 @@ static void cqspi_remove(struct platform_device *pde= v) cqspi_jh7110_disable_clk(pdev, cqspi); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - if (pm_runtime_get_sync(&pdev->dev) >=3D 0) - clk_disable(cqspi->clk); + ret =3D pm_runtime_get_sync(&pdev->dev); + + if (ret >=3D 0) + clk_disable(cqspi->clk); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6135C36D51C; Thu, 15 Jan 2026 09:25:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469154; cv=none; b=UIs2oFaGr3X26p+GOq0/H9tgSGpINgU2JyAOP5utCHg7zZtJSe1eBl/h/R0kaYqccNg1cF1pAgMyvQ7jOcjcnY60e/fQngK1BFCImRjF7eonpMZ7NEUIrzHMmeIoOab/P5XtCrvlyG0z7K9W3t3GMWBv89CKX91JWdHOvdiRIKM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469154; c=relaxed/simple; bh=YpDz/vG3DLbjkSP8w4hH9fZsadfIh0jV+dj16U2Mki4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YaolgdmvdoFM8CaBGjFGOcecwK/S9sgMavNzgUk2hHIts9J45l6zMJMItMZQhjMINHqwgCX9dkMjwfe8Ic1lI3Hi6jjGB0YggmbV3iMO+V2LMoj27VzzUaFSIzwQ2lTF4c5tFPJbNs+NPXflAlJCnTZ+LHBqdqnug032aY/nPHo= ARC-Authentication-Results: i=1; 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Thu, 15 Jan 2026 10:25:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469149; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=m2OlrB1WHxCAT8bt6bn0v6vCet93lc8eeCwRus+Rn4A=; b=fyJTSoCa/xmuWaNWYHiuD3d6R8B3Gs1Qxq+IlyvQMrpPe/xdcNHB6JzEB/KRSX36dPpiS1 NrwAyLACwTCRLosCoW19rlJCKhCQkf+SDi6nqN287hUa9pB6mUZZ6jPqcTNNGmatVvQMLK /Lu3udZQrB8htsitlc2CesheJbeaSYePx39BJ6ica7XXxrSK0A5CVpEwbcFkrD/DncRkk0 9HSa/d2yr5Zqzo73SnBE8rWU6sbjOQncCdpZtTTQskh+K3uz8om1FBk6plsX6+zSyzzSZF yIdJjfHOavoCba3oOGPE6QZNxVA08PZsH3VHl7HN0QrWZj6WAG0s9xkIuQ7GHQ== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:25:00 +0100 Subject: [PATCH v2 09/13] spi: cadence-qspi: Kill cqspi_jh7110_clk_init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-9-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This controller can be fed by either a main "ref" clock, or three clocks ("ref" again, "ahb", "apb"). In practice, it is likely that all controllers have the same inputs, but a single clock feeds the three interfaces (ref is used for controlling the external interface, ahb/apb the internal ones). Handling these clocks is in no way SoC specific, only the number of expected clocks may change. Plus, we will soon be adding another controller requiring an AHB and an APB clock as well, so it is time to align the whole clock handling. Furthermore, the use of the cqspi_jh7110_clk_init() helper, which specifically grabs and enables the "ahb" and "apb" clocks, is a bit convoluted: - only the JH7110 compatible provides the ->jh7110_clk_init() callback, - in the probe, if the above callback is set in the driver data, the driver does not call the callback (!) but instead calls the helper directly (?), - in the helper, the is_jh7110 boolean is set. This logic does not make sense. Instead: - in the probe, set the is_jh7110 boolean based on the compatible, - collect all available clocks with the "bulk" helper, - enable the extra clocks if they are available, - kill the SoC specific cqspi_jh7110_clk_init() helper. This also allows to group the clock handling instead of depending on the driver data pointer, which further simplifies the error path and the remove callback. Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 120 ++++++++++++----------------------= ---- 1 file changed, 37 insertions(+), 83 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index af0ad24d8d39..e389422fe95e 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -55,7 +55,8 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) =20 enum { - CLK_QSPI_APB =3D 0, + CLK_QSPI_REF =3D 0, + CLK_QSPI_APB, CLK_QSPI_AHB, CLK_QSPI_NUM, }; @@ -76,8 +77,7 @@ struct cqspi_flash_pdata { struct cqspi_st { struct platform_device *pdev; struct spi_controller *host; - struct clk *clk; - struct clk *clks[CLK_QSPI_NUM]; + struct clk_bulk_data clks[CLK_QSPI_NUM]; unsigned int sclk; =20 void __iomem *iobase; @@ -121,8 +121,6 @@ struct cqspi_driver_platdata { int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx); u32 (*get_dma_status)(struct cqspi_st *cqspi); - int (*jh7110_clk_init)(struct platform_device *pdev, - struct cqspi_st *cqspi); }; =20 /* Operation timeout value */ @@ -1763,61 +1761,20 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) return 0; } =20 -static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqsp= i_st *cqspi) -{ - static struct clk_bulk_data qspiclk[] =3D { - { .id =3D "apb" }, - { .id =3D "ahb" }, - }; - - int ret =3D 0; - - ret =3D devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); - if (ret) { - dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); - return ret; - } - - cqspi->clks[CLK_QSPI_APB] =3D qspiclk[0].clk; - cqspi->clks[CLK_QSPI_AHB] =3D qspiclk[1].clk; - - ret =3D clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); - if (ret) { - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); - return ret; - } - - ret =3D clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); - if (ret) { - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); - goto disable_apb_clk; - } - - cqspi->is_jh7110 =3D true; - - return 0; - -disable_apb_clk: - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); - - return ret; -} - -static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct = cqspi_st *cqspi) -{ - clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); -} static int cqspi_probe(struct platform_device *pdev) { const struct cqspi_driver_platdata *ddata; struct reset_control *rstc, *rstc_ocp, *rstc_ref; + static const char *clk_ids[CLK_QSPI_NUM] =3D { + [CLK_QSPI_REF] =3D "ref", + [CLK_QSPI_APB] =3D "apb", + [CLK_QSPI_AHB] =3D "ahb", + }; struct device *dev =3D &pdev->dev; struct spi_controller *host; struct resource *res_ahb; struct cqspi_st *cqspi; - int ret; - int irq; + int ret, i, irq; =20 host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); if (!host) @@ -1829,10 +1786,11 @@ static int cqspi_probe(struct platform_device *pdev) host->dev.of_node =3D pdev->dev.of_node; =20 cqspi =3D spi_controller_get_devdata(host); + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) + cqspi->is_jh7110 =3D true; =20 cqspi->pdev =3D pdev; cqspi->host =3D host; - cqspi->is_jh7110 =3D false; cqspi->ddata =3D ddata =3D of_device_get_match_data(dev); platform_set_drvdata(pdev, cqspi); =20 @@ -1849,12 +1807,17 @@ static int cqspi_probe(struct platform_device *pdev) return ret; } =20 - /* Obtain QSPI clock. */ - cqspi->clk =3D devm_clk_get(dev, NULL); - if (IS_ERR(cqspi->clk)) { - dev_err(dev, "Cannot claim QSPI clock.\n"); - ret =3D PTR_ERR(cqspi->clk); - return ret; + /* Obtain QSPI clocks. */ + for (i =3D 0; i < CLK_QSPI_NUM; ++i) + cqspi->clks[i].id =3D clk_ids[i]; + + ret =3D devm_clk_bulk_get_optional(dev, CLK_QSPI_NUM, cqspi->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); + + if (!cqspi->clks[CLK_QSPI_REF].clk) { + dev_err(dev, "Cannot claim mandatory QSPI ref clock.\n"); + return -ENODEV; } =20 /* Obtain and remap controller address. */ @@ -1886,10 +1849,9 @@ static int cqspi_probe(struct platform_device *pdev) if (ret) return ret; =20 - - ret =3D clk_prepare_enable(cqspi->clk); + ret =3D clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); if (ret) { - dev_err(dev, "Cannot enable QSPI clock.\n"); + dev_err(dev, "Cannot enable QSPI clocks.\n"); goto disable_rpm; } =20 @@ -1898,22 +1860,22 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc)) { ret =3D PTR_ERR(rstc); dev_err(dev, "Cannot get QSPI reset.\n"); - goto disable_clk; + goto disable_clks; } =20 rstc_ocp =3D devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); if (IS_ERR(rstc_ocp)) { ret =3D PTR_ERR(rstc_ocp); dev_err(dev, "Cannot get QSPI OCP reset.\n"); - goto disable_clk; + goto disable_clks; } =20 - if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { + if (cqspi->is_jh7110) { rstc_ref =3D devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); if (IS_ERR(rstc_ref)) { ret =3D PTR_ERR(rstc_ref); dev_err(dev, "Cannot get QSPI REF reset.\n"); - goto disable_clk; + goto disable_clks; } reset_control_assert(rstc_ref); reset_control_deassert(rstc_ref); @@ -1925,7 +1887,7 @@ static int cqspi_probe(struct platform_device *pdev) reset_control_assert(rstc_ocp); reset_control_deassert(rstc_ocp); =20 - cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clk); + cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); host->max_speed_hz =3D cqspi->master_ref_clk_hz; =20 /* write completion is supported by default */ @@ -1951,12 +1913,6 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->slow_sram =3D true; if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) cqspi->apb_ahb_hazard =3D true; - - if (ddata->jh7110_clk_init) { - ret =3D cqspi_jh7110_clk_init(pdev, cqspi); - if (ret) - goto disable_clk; - } if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) cqspi->disable_stig_mode =3D true; =20 @@ -2022,11 +1978,8 @@ static int cqspi_probe(struct platform_device *pdev) disable_controller: cqspi_controller_enable(cqspi, 0); disable_clks: - if (cqspi->is_jh7110) - cqspi_jh7110_disable_clk(pdev, cqspi); -disable_clk: if (pm_runtime_get_sync(&pdev->dev) >=3D 0) - clk_disable_unprepare(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); disable_rpm: if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) pm_runtime_disable(dev); @@ -2055,14 +2008,12 @@ static void cqspi_remove(struct platform_device *pd= ev) =20 cqspi_controller_enable(cqspi, 0); =20 - if (cqspi->is_jh7110) - cqspi_jh7110_disable_clk(pdev, cqspi); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) ret =3D pm_runtime_get_sync(&pdev->dev); =20 if (ret >=3D 0) - clk_disable(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); @@ -2075,15 +2026,19 @@ static int cqspi_runtime_suspend(struct device *dev) struct cqspi_st *cqspi =3D dev_get_drvdata(dev); =20 cqspi_controller_enable(cqspi, 0); - clk_disable_unprepare(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); return 0; } =20 static int cqspi_runtime_resume(struct device *dev) { struct cqspi_st *cqspi =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); + if (ret) + return ret; =20 - clk_prepare_enable(cqspi->clk); cqspi_wait_idle(cqspi); cqspi_controller_enable(cqspi, 0); cqspi_controller_init(cqspi); @@ -2166,7 +2121,6 @@ static const struct cqspi_driver_platdata versal2_osp= i =3D { =20 static const struct cqspi_driver_platdata jh7110_qspi =3D { .quirks =3D CQSPI_DISABLE_DAC_MODE, - .jh7110_clk_init =3D cqspi_jh7110_clk_init, }; =20 static const struct cqspi_driver_platdata pensando_cdns_qspi =3D { --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E28A93803C9; Thu, 15 Jan 2026 09:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="EYYdaoyY" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 951401A287A; Thu, 15 Jan 2026 09:25:52 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6CA0F606B6; Thu, 15 Jan 2026 09:25:52 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CCFAA10B68531; Thu, 15 Jan 2026 10:25:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469151; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=+hBnNkivyv+n3X/ChkXKt4HpdgNECvLrCvfE+vU0L00=; b=EYYdaoyYp+DU+AlCtUod95q8Gkq9YlAkUAjyJRx8TCwib0C0IIH/2R22bNot9JhPcfVNsU 3qnTXyHSQSQMB7Z7rVftopMWZw7qoaSoQYzQFYYuM5kT/0UtYDQyo+XHmIU+V9YtSP96oE bOUworhGtdXg9n6QhVxFRJIZOnaQxvoYzQbSUvFne//NNoo2oVqNdAWpmD7AgQ08/YYwKe DBf+g9xAmf6fP2eQgu0mY61naZlDeW3tfgLMDP16b+tki5YggSnyFlrKdNQHwyNcf8wiz4 FRbR0VxYoPeBvIouk1ZMRocbZBOM0bbiUs7fDDAZe2Unxjl6uzoe7Jd0qUbDvg== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:25:01 +0100 Subject: [PATCH v2 10/13] spi: cadence-qspi: Add a flag for controllers without indirect access support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-10-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed the Cadence IP with some limitations/simplifications. One of the is that only direct access is supported, none of the registers related to indirect writes are populated, so create a flag to avoid these accesses and make sure only direct accessors are called. Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index e389422fe95e..d84531aa470c 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -47,6 +47,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_SUPPORT_DEVICE_RESET BIT(8) #define CQSPI_DISABLE_STIG_MODE BIT(9) #define CQSPI_DISABLE_RUNTIME_PM BIT(10) +#define CQSPI_NO_INDIRECT_MODE BIT(11) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -1423,7 +1424,8 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f= _pdata, if (ret) return ret; =20 - if (cqspi->use_direct_mode && ((from + len) <=3D cqspi->ahb_size)) + if ((cqspi->use_direct_mode && ((from + len) <=3D cqspi->ahb_size)) || + (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) return cqspi_direct_read_execute(f_pdata, buf, from, len); =20 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && @@ -1624,19 +1626,20 @@ static void cqspi_controller_init(struct cqspi_st *= cqspi) /* Disable all interrupts. */ writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); =20 - /* Configure the SRAM split to 1:1 . */ - writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); + if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { + /* Configure the SRAM split to 1:1 . */ + writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); + /* Load indirect trigger address. */ + writel(cqspi->trigger_address, + cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); =20 - /* Load indirect trigger address. */ - writel(cqspi->trigger_address, - cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); - - /* Program read watermark -- 1/2 of the FIFO. */ - writel(cqspi->fifo_depth * cqspi->fifo_width / 2, - cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); - /* Program write watermark -- 1/8 of the FIFO. */ - writel(cqspi->fifo_depth * cqspi->fifo_width / 8, - cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); + /* Program read watermark -- 1/2 of the FIFO. */ + writel(cqspi->fifo_depth * cqspi->fifo_width / 2, + cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); + /* Program write watermark -- 1/8 of the FIFO. */ + writel(cqspi->fifo_depth * cqspi->fifo_width / 8, + cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); + } =20 /* Disable direct access controller */ if (!cqspi->use_direct_mode) { --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 139EE389E1A; Thu, 15 Jan 2026 09:25:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469157; cv=none; b=Em43LTb2ZCuy6y7KtvQCuYCxUX5pkJw+Cy/N8+C7/t1hPJ1C6CjjKTV32Ms/FC8jMdpQ0CnhMc/XgHQugEx555WvS4+IBXqAMnYEMDkCmlMURB1J8rElnW15Rk2+n3hJFdzZ1ENUzIPrArmxJAqHcseqSOXz3MtbsMSRLndfEpc= ARC-Message-Signature: i=1; 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Thu, 15 Jan 2026 09:25:28 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CA5B2606B6; Thu, 15 Jan 2026 09:25:54 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D8B4B10B6852D; Thu, 15 Jan 2026 10:25:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469153; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=+LL3KeG0p9hrIlsBrxn1Y7duS7uVUzLvSPr2dOdaikI=; b=Vgyhb7k6Nqh6oF0QrSDrNPCv3jrxtFiHkcr6c8Mz2QJDE8+nZVMTVWWb1eyWR5Z/H4Zi/R YFB1rPkb1UFJ6j+ME/jg1Vgyzq0JYDSGHp41t8VRpDqpYnScS4NTu2qE+TjI4EJFSCu8i6 x256iLxdKrEqK4J+CZSPhrTxiSXA/8KRpp4f/nfOS2mJeI+Ts5zm+/maQ1l2ire9zl/TVg YRluL8hGDdYWM75QYSLsm/kxMmFVHR9oxtlEBMJsLYJCGQAOgTtwKHTeCHeO5WSpOVt4Ta 7EfG0aN6J2AE9NwFWEJHMG0Kk7HFec3QT2UuoZKvlvIdTJ5MVsz1L30AKpzg2Q== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:25:02 +0100 Subject: [PATCH v2 11/13] spi: cadence-qspi: Make sure write protection is disabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-11-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed the Cadence IP with some modifications. For instance, they feature a write protection of the direct mapping at the controller level, with this feature all data writes to the AHB region are aborted. Despite the fact that the flag setting write protection is disabled by default, Bootloaders may (and actually do) set it, so mark this feature as being available with a specific flag to, if applicable, make sure it is disabled. Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- drivers/spi/spi-cadence-quadspi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index d84531aa470c..fc7e64614a32 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -48,6 +48,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_DISABLE_STIG_MODE BIT(9) #define CQSPI_DISABLE_RUNTIME_PM BIT(10) #define CQSPI_NO_INDIRECT_MODE BIT(11) +#define CQSPI_HAS_WR_PROTECT BIT(12) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -218,6 +219,8 @@ struct cqspi_driver_platdata { #define CQSPI_REG_IRQSTATUS 0x40 #define CQSPI_REG_IRQMASK 0x44 =20 +#define CQSPI_REG_WR_PROT_CTRL 0x58 + #define CQSPI_REG_INDIRECTRD 0x60 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) @@ -1641,6 +1644,10 @@ static void cqspi_controller_init(struct cqspi_st *c= qspi) cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); } =20 + /* Disable write protection at controller level */ + if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_HAS_WR_PROTECT) + writel(0, cqspi->iobase + CQSPI_REG_WR_PROT_CTRL); + /* Disable direct access controller */ if (!cqspi->use_direct_mode) { reg =3D readl(cqspi->iobase + CQSPI_REG_CONFIG); --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E47613803C9; Thu, 15 Jan 2026 09:25:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469160; cv=none; b=ozBq1j4F3ZfZgDXW57wMfH0LVwCz1Ws/mDwP9Jn9bc4oegJGHnob9XGe2vY5rX/hNkThuft3nAc/M9XwkLaytwWE5ecLMjow04Yepq4ivvpHr7oufSOd34dQuvRp9UDdVTUWFjs2meBE3CXXhJVYPFbg20FViXW7MSRUQafdbQI= ARC-Message-Signature: i=1; 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Thu, 15 Jan 2026 09:25:57 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 37E42606B6; Thu, 15 Jan 2026 09:25:57 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0956510B68534; Thu, 15 Jan 2026 10:25:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768469155; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=rHT4Vl1bgtyP2vv8Z5ShLUQ7VoFtQgXFMIkmV8U1sY0=; b=t4VmVLNSP16vvuHkNci6S91sGep7d585qlJ/elt6Y3GItJNZxdlNPEGuSuX/LK3sDvrFlE 4oJEWjnbSNARzuzzPcGzbHPwv3CXfEyoQxYYI9MzloubZKYtaYFB+V8ibiZsWklbzZ4N3i w4NU3dyDTpFAGOzGIVcC8LkB6xmocMeWvhWguG96U2BqgTe42fZl51hVsnbA1K/TaNbfjz fak+BAhcJkvgd2uc6LJxaBgCkg6NXvapMCCh8gTNoT7AKNbM2f+QNDJePR80omZ0VkFWA1 Q7Xez+90h0dHHpM2z76q+TMH+isc18bOKsXTlS10XRiy36JIlUNnwYHjipqcCQ== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:25:03 +0100 Subject: [PATCH v2 12/13] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-12-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed a modified version of the Cadence IP with the following settings: - a limited bus clock range - no DTR support - no DMA - no useful interrupt flag - only direct accesses (no INDAC mode) - write protection The controller has been tested by running the SPI NOR check list with a custom RZ/N1D400 based board mounted with a Spansion s25fl128s1 quad SPI. Signed-off-by: Miquel Raynal (Schneider Electric) Tested-by: Wolfram Sang --- Output of the SPI NOR test procedure: s25fl128s1 0120184d0180 spansion xxd: /sys/bus/spi/devices/spi0.0/spi-nor/sfdp: No such file or directory md5sum: can't open '/sys/bus/spi/devices/spi0.0/spi-nor/sfdp': No such file= or directory 1+0 records in 1+0 records out Copied 65536 bytes from qspi_test to address 0x00000000 in flash Erased 65536 bytes from address 0x00000000 in flash Copied 65536 bytes from address 0x00000000 in flash to qspi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0010000 Copied 65536 bytes from qspi_test to address 0x00000000 in flash Copied 65536 bytes from address 0x00000000 in flash to qspi_read 71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_test 71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_read Read speed: * page read speed is 6464 KiB/s * 2 page read speed is 9014 KiB/s * eraseblock read speed is 14222 KiB/s Write speed: * page write speed is 621 KiB/s * 2 page write speed is 626 KiB/s * eraseblock write speed is 633 KiB/s Erase speed: * erase speed is 617 KiB/s --- drivers/spi/spi-cadence-quadspi.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index fc7e64614a32..297336f51360 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -110,6 +110,7 @@ struct cqspi_st { bool apb_ahb_hazard; =20 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ + bool is_rzn1; /* Flag for Renesas RZN1 SoC */ bool disable_stig_mode; refcount_t refcount; refcount_t inflight_ops; @@ -1337,8 +1338,9 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *= f_pdata, * mode. So, we can not use direct mode when in DTR mode for writing * data. */ - if (!op->cmd.dtr && cqspi->use_direct_mode && - cqspi->use_direct_mode_wr && ((to + len) <=3D cqspi->ahb_size)) { + if ((!op->cmd.dtr && cqspi->use_direct_mode && + cqspi->use_direct_mode_wr && ((to + len) <=3D cqspi->ahb_size)) || + (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { memcpy_toio(cqspi->ahb_base + to, buf, len); return cqspi_wait_idle(cqspi); } @@ -1512,6 +1514,7 @@ static int cqspi_exec_mem_op(struct spi_mem *mem, con= st struct spi_mem_op *op) static bool cqspi_supports_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { + struct cqspi_st *cqspi =3D spi_controller_get_devdata(mem->spi->controlle= r); bool all_true, all_false; =20 /* @@ -1538,6 +1541,9 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, /* A single opcode is supported, it will be repeated */ if ((op->cmd.opcode >> 8) !=3D (op->cmd.opcode & 0xFF)) return false; + + if (cqspi->is_rzn1) + return false; } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; @@ -1798,6 +1804,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi =3D spi_controller_get_devdata(host); if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) cqspi->is_jh7110 =3D true; + if (of_device_is_compatible(pdev->dev.of_node, "renesas,rzn1-qspi")) + cqspi->is_rzn1 =3D true; =20 cqspi->pdev =3D pdev; cqspi->host =3D host; @@ -1898,7 +1906,12 @@ static int cqspi_probe(struct platform_device *pdev) reset_control_deassert(rstc_ocp); =20 cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); - host->max_speed_hz =3D cqspi->master_ref_clk_hz; + if (!cqspi->is_rzn1) { + host->max_speed_hz =3D cqspi->master_ref_clk_hz; + } else { + host->max_speed_hz =3D cqspi->master_ref_clk_hz / 2; + host->min_speed_hz =3D cqspi->master_ref_clk_hz / 32; + } =20 /* write completion is supported by default */ cqspi->wr_completion =3D true; @@ -1963,7 +1976,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)) cqspi_device_reset(cqspi); =20 - if (cqspi->use_direct_mode) { + if (cqspi->use_direct_mode && !cqspi->is_rzn1) { ret =3D cqspi_request_mmap_dma(cqspi); if (ret =3D=3D -EPROBE_DEFER) { dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n"); @@ -2143,6 +2156,12 @@ static const struct cqspi_driver_platdata mobileye_e= yeq5_ospi =3D { CQSPI_RD_NO_IRQ, }; =20 +static const struct cqspi_driver_platdata renesas_rzn1_qspi =3D { + .hwcaps_mask =3D CQSPI_SUPPORTS_QUAD, + .quirks =3D CQSPI_NO_SUPPORT_WR_COMPLETION | CQSPI_RD_NO_IRQ | + CQSPI_HAS_WR_PROTECT | CQSPI_NO_INDIRECT_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] =3D { { .compatible =3D "cdns,qspi-nor", @@ -2184,6 +2203,10 @@ static const struct of_device_id cqspi_dt_ids[] =3D { .compatible =3D "amd,versal2-ospi", .data =3D &versal2_ospi, }, + { + .compatible =3D "renesas,rzn1-qspi", + .data =3D &renesas_rzn1_qspi, + }, { /* end of table */ } }; =20 --=20 2.51.1 From nobody Mon Feb 9 10:42:35 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59B3F38BF83; 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bh=cFZyearDwfGg052H4Xsc1MdeOqI5t0yhI+26mZIpcUc=; b=USgq+H6bezJJvaGnpRvxviSTVz7f0zqozBk0BVIrNOYq5sAq/9RNSTKsiPsfDDC4IcTbgC WrvC92Bxp6ROFwuCMTVQUeSa7fHf/Nzl5vIED28SDFhN3uOkjTBV/+BBE15DMtZb+2Xx9T IAo0Q6Ml/pA506sAJy+XKM8AktQCKvN7UIceiPYUc/34a4zTcURxmn+ymVPQ9b62lHnVxq HhoZ0YaWakopuh9Nn6wp6weRe6tnqz1FeJBKeLh5y3zxde6zZxfvr+awivdlnlzNXhqD7o thY0AewXXuR58ijMjmO2gDN2PrM40O8zCWW1Fu5DpaWIox4QKfqwF+SWAdK0gQ== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 15 Jan 2026 10:25:04 +0100 Subject: [PATCH v2 13/13] ARM: dts: r9a06g032: Describe the QSPI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-schneider-6-19-rc1-qspi-v2-13-7e6a06e1e17b@bootlin.com> References: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> In-Reply-To: <20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add a node describing the QSPI controller. There are 2 clocks feeding this controller: - one for the reference clock - one that feeds both the ahb and the apb interfaces As the binding expect either the ref clock, or all three (ref, ahb and apb) clocks, it makes sense to provide the same clock twice. Signed-off-by: Miquel Raynal (Schneider Electric) Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 8debb77803bb..802db8d74178 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -66,6 +66,20 @@ soc { #size-cells =3D <1>; ranges; =20 + qspi0: spi@40005000 { + compatible =3D "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qsp= i-nor"; + reg =3D <0x40005000 0x1000>, <0x10000000 0x10000000>; + interrupts =3D ; + clocks =3D <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSP= I0>, + <&sysctrl R9A06G032_HCLK_QSPI0>; + clock-names =3D "ref", "ahb", "apb"; + #address-cells =3D <1>; + #size-cells =3D <0>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0>; + status =3D "disabled"; + }; + rtc0: rtc@40006000 { compatible =3D "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; reg =3D <0x40006000 0x1000>; --=20 2.51.1