On Tue, 2025-12-30 at 11:03 -0300, Nícolas F. R. A. Prado wrote:
> Despite MT8188's OVL being mostly the same IP as the OVL on MT8195, it
> does not support AFBC, even when the same register configurations are
> applied. Introduce a separate compatible for it with AFBC support
> disabled.
>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 196b874057ba..97f6694772d4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -762,6 +762,21 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
> .num_formats = ARRAY_SIZE(mt8173_formats),
> };
>
> +static const struct mtk_disp_ovl_data mt8188_ovl_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 4,
> + .fmt_rgb565_is_0 = true,
> + .smi_id_en = true,
> + .supports_afbc = false,
Global variable is initialized to zero, so this could be drop.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
> + .blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
> + BIT(DRM_MODE_BLEND_COVERAGE) |
> + BIT(DRM_MODE_BLEND_PIXEL_NONE),
> + .formats = mt8195_formats,
> + .num_formats = ARRAY_SIZE(mt8195_formats),
> + .supports_clrfmt_ext = true,
> +};
> +
> static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT8173,
> .gmc_bits = 10,
> @@ -790,6 +805,8 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> .data = &mt8192_ovl_driver_data},
> { .compatible = "mediatek,mt8192-disp-ovl-2l",
> .data = &mt8192_ovl_2l_driver_data},
> + { .compatible = "mediatek,mt8188-disp-ovl",
> + .data = &mt8188_ovl_driver_data},
> { .compatible = "mediatek,mt8195-disp-ovl",
> .data = &mt8195_ovl_driver_data},
> {},
>