Add a simple regmap-based clk_ops implementation for Realtek mux clocks.
The implementation supports parent selection and rate determination through
regmap-backed register access.
Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
---
drivers/clk/realtek/Makefile | 1 +
drivers/clk/realtek/clk-regmap-mux.c | 46 ++++++++++++++++++++++++++++
drivers/clk/realtek/clk-regmap-mux.h | 43 ++++++++++++++++++++++++++
3 files changed, 90 insertions(+)
create mode 100644 drivers/clk/realtek/clk-regmap-mux.c
create mode 100644 drivers/clk/realtek/clk-regmap-mux.h
diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
index 97058d48a176..b40dd5a26653 100644
--- a/drivers/clk/realtek/Makefile
+++ b/drivers/clk/realtek/Makefile
@@ -5,5 +5,6 @@ clk-rtk-y += common.o
clk-rtk-y += clk-pll.o
clk-rtk-y += clk-regmap-gate.o
+clk-rtk-y += clk-regmap-mux.o
clk-rtk-y += freq_table.o
clk-rtk-y += reset.o
diff --git a/drivers/clk/realtek/clk-regmap-mux.c b/drivers/clk/realtek/clk-regmap-mux.c
new file mode 100644
index 000000000000..10f677b3f26d
--- /dev/null
+++ b/drivers/clk/realtek/clk-regmap-mux.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2017 Realtek Semiconductor Corporation
+ * Author: Cheng-Yu Lee <cylee12@realtek.com>
+ */
+
+#include "clk-regmap-mux.h"
+
+static u8 clk_regmap_mux_get_parent(struct clk_hw *hw)
+{
+ struct clk_regmap_mux *clkm = to_clk_regmap_mux(hw);
+ int num_parents = clk_hw_get_num_parents(hw);
+ u32 val;
+ int ret;
+
+ ret = regmap_read(clkm->clkr.regmap, clkm->mux_ofs, &val);
+ if (ret)
+ return ret;
+
+ val = val >> clkm->shift & clkm->mask;
+
+ if (val >= num_parents)
+ return -EINVAL;
+
+ return val;
+}
+
+static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_regmap_mux *clkm = to_clk_regmap_mux(hw);
+
+ return regmap_update_bits(clkm->clkr.regmap, clkm->mux_ofs,
+ clkm->mask << clkm->shift, index << clkm->shift);
+}
+
+const struct clk_ops clk_regmap_mux_ops = {
+ .set_parent = clk_regmap_mux_set_parent,
+ .get_parent = clk_regmap_mux_get_parent,
+ .determine_rate = __clk_mux_determine_rate,
+};
+EXPORT_SYMBOL_GPL(clk_regmap_mux_ops);
+
+const struct clk_ops clk_regmap_mux_ro_ops = {
+ .get_parent = clk_regmap_mux_get_parent,
+};
+EXPORT_SYMBOL_GPL(clk_regmap_mux_ro_ops);
diff --git a/drivers/clk/realtek/clk-regmap-mux.h b/drivers/clk/realtek/clk-regmap-mux.h
new file mode 100644
index 000000000000..4855d4e94bc2
--- /dev/null
+++ b/drivers/clk/realtek/clk-regmap-mux.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2017 Realtek Semiconductor Corporation
+ * Author: Cheng-Yu Lee <cylee12@realtek.com>
+ */
+
+#ifndef __CLK_REALTEK_CLK_REGMAP_MUX_H
+#define __CLK_REALTEK_CLK_REGMAP_MUX_H
+
+#include "common.h"
+
+struct clk_regmap_mux {
+ struct clk_regmap clkr;
+ int mux_ofs;
+ unsigned int mask;
+ unsigned int shift;
+};
+
+#define __clk_regmap_mux_hw(_p) __clk_regmap_hw(&(_p)->clkr)
+
+#define __CLK_REGMAP_MUX(_name, _parents, _ops, _flags, _ofs, _sft, _mask) \
+ struct clk_regmap_mux _name = { \
+ .clkr.hw.init = \
+ CLK_HW_INIT_PARENTS(#_name, _parents, _ops, _flags), \
+ .mux_ofs = _ofs, \
+ .shift = _sft, \
+ .mask = _mask, \
+ }
+
+#define CLK_REGMAP_MUX(_name, _parents, _flags, _ofs, _sft, _mask) \
+ __CLK_REGMAP_MUX(_name, _parents, &clk_regmap_mux_ops, _flags, _ofs, \
+ _sft, _mask)
+
+static inline struct clk_regmap_mux *to_clk_regmap_mux(struct clk_hw *hw)
+{
+ struct clk_regmap *clkr = to_clk_regmap(hw);
+
+ return container_of(clkr, struct clk_regmap_mux, clkr);
+}
+
+extern const struct clk_ops clk_regmap_mux_ops;
+
+#endif /* __CLK_REALTEK_CLK_REGMAP_MUX_H */
--
2.34.1Hi Yu-Chun,
kernel test robot noticed the following build warnings:
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Yu-Chun-Lin/dt-bindings-clock-Add-Realtek-RTD1625-Clock-Reset-Controller/20251229-155549
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link: https://lore.kernel.org/r/20251229075313.27254-7-eleanor.lin%40realtek.com
patch subject: [PATCH 6/9] clk: realtek: Add support for mux clock
config: loongarch-randconfig-r072-20251231 (https://download.01.org/0day-ci/archive/20251231/202512310307.swVDgnPU-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 12.5.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202512310307.swVDgnPU-lkp@intel.com/
smatch warnings:
drivers/clk/realtek/clk-regmap-mux.c:23 clk_regmap_mux_get_parent() warn: signedness bug returning '(-22)'
vim +23 drivers/clk/realtek/clk-regmap-mux.c
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 9 static u8 clk_regmap_mux_get_parent(struct clk_hw *hw)
^^
This function returns negative error codes so it needs to be type int.
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 10 {
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 11 struct clk_regmap_mux *clkm = to_clk_regmap_mux(hw);
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 12 int num_parents = clk_hw_get_num_parents(hw);
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 13 u32 val;
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 14 int ret;
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 15
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 16 ret = regmap_read(clkm->clkr.regmap, clkm->mux_ofs, &val);
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 17 if (ret)
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 18 return ret;
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 19
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 20 val = val >> clkm->shift & clkm->mask;
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 21
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 22 if (val >= num_parents)
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 @23 return -EINVAL;
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 24
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 25 return val;
f53de7a7df69f0 Yu-Chun Lin 2025-12-29 26 }
--
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