From nobody Mon Feb 9 09:09:48 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 972BE26B2B0; Mon, 29 Dec 2025 07:53:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766994824; cv=none; b=ac0u0aVuqb4i6fLNglXrI/smxI4bxOVBGu5oisDHLM1GL+EhyAoqVWTFeuMCqFZHZzMtWV/rCD5u9HPAdUb6GbcHGg6jhxLIyxPLtMkVhY4YK/a9iYJqlLVxzemgUdRKUZssw3vAmGr78huyBwdNHXZqtbgRJ/8yI0d5eF69RSY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766994824; c=relaxed/simple; bh=YgmJflvxcG7SaFwwjTMIAHGqX1/IXiAbKL0Hvh3NuTk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DUGW9M4cPlmfINJFbSCMhnLw72KMrLf/sLKVo93YLI0H4L8llGtEAbyftBq6hVhg+zyEm/S4aHAWF4bjVDjchg/7Mi5Wo6d6xO2hzxoxvG/pGng/DMjgQq9Vc19460JKV0KkWjhYyO8yUtuJp8gZSxikT7ZXkiI0bnIj2xDLyIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=SV6SjACd; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="SV6SjACd" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 5BT7rFLC1703577, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1766994795; bh=UK2vAjkCaEuiztkh4LmrEe2NXZ4ZmYX6ETvDrBq1tQc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=SV6SjACdBM0Px6+aSgQXSQlOY8GMDuWUniv90l2ThQ84i7/4nD18mtwnODH6wN8Iy 9SoUMLyxIToASFDWuejBloDtytxwCUm2cMEgez1vhcWR/ygmGiNh0K4qaCf1tWgfL7 kFry47letGQ6AQpZrE4CUHwMjMvTT61uBTaFVzz6ULXAbnpjqSZ6Aj9h6CJjuyVEWi Dx7tTWIUBymFQ3JZNvv1KieJpGdBruTouomSgWoK+7kByZloAN4g6GCvDuZ5et+bN2 saMZB/E6xosuxjueTpTLugxLwVCn2yFdi5DUm8T3DgADcqSOEO9GjVGTetLiDJu27c bSyFwQzB6zAgQ== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 5BT7rFLC1703577 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 29 Dec 2025 15:53:15 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 29 Dec 2025 15:53:15 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 29 Dec 2025 15:53:15 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 29 Dec 2025 15:53:15 +0800 From: Yu-Chun Lin To: , , , , , , , CC: , , , , , , Subject: [PATCH 6/9] clk: realtek: Add support for mux clock Date: Mon, 29 Dec 2025 15:53:10 +0800 Message-ID: <20251229075313.27254-7-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251229075313.27254-1-eleanor.lin@realtek.com> References: <20251229075313.27254-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a simple regmap-based clk_ops implementation for Realtek mux clocks. The implementation supports parent selection and rate determination through regmap-backed register access. Signed-off-by: Cheng-Yu Lee Signed-off-by: Yu-Chun Lin --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-regmap-mux.c | 46 ++++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-mux.h | 43 ++++++++++++++++++++++++++ 3 files changed, 90 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-mux.c create mode 100644 drivers/clk/realtek/clk-regmap-mux.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 97058d48a176..b40dd5a26653 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -5,5 +5,6 @@ clk-rtk-y +=3D common.o =20 clk-rtk-y +=3D clk-pll.o clk-rtk-y +=3D clk-regmap-gate.o +clk-rtk-y +=3D clk-regmap-mux.o clk-rtk-y +=3D freq_table.o clk-rtk-y +=3D reset.o diff --git a/drivers/clk/realtek/clk-regmap-mux.c b/drivers/clk/realtek/clk= -regmap-mux.c new file mode 100644 index 000000000000..10f677b3f26d --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-mux.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include "clk-regmap-mux.h" + +static u8 clk_regmap_mux_get_parent(struct clk_hw *hw) +{ + struct clk_regmap_mux *clkm =3D to_clk_regmap_mux(hw); + int num_parents =3D clk_hw_get_num_parents(hw); + u32 val; + int ret; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->mux_ofs, &val); + if (ret) + return ret; + + val =3D val >> clkm->shift & clkm->mask; + + if (val >=3D num_parents) + return -EINVAL; + + return val; +} + +static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_regmap_mux *clkm =3D to_clk_regmap_mux(hw); + + return regmap_update_bits(clkm->clkr.regmap, clkm->mux_ofs, + clkm->mask << clkm->shift, index << clkm->shift); +} + +const struct clk_ops clk_regmap_mux_ops =3D { + .set_parent =3D clk_regmap_mux_set_parent, + .get_parent =3D clk_regmap_mux_get_parent, + .determine_rate =3D __clk_mux_determine_rate, +}; +EXPORT_SYMBOL_GPL(clk_regmap_mux_ops); + +const struct clk_ops clk_regmap_mux_ro_ops =3D { + .get_parent =3D clk_regmap_mux_get_parent, +}; +EXPORT_SYMBOL_GPL(clk_regmap_mux_ro_ops); diff --git a/drivers/clk/realtek/clk-regmap-mux.h b/drivers/clk/realtek/clk= -regmap-mux.h new file mode 100644 index 000000000000..4855d4e94bc2 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-mux.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_MUX_H +#define __CLK_REALTEK_CLK_REGMAP_MUX_H + +#include "common.h" + +struct clk_regmap_mux { + struct clk_regmap clkr; + int mux_ofs; + unsigned int mask; + unsigned int shift; +}; + +#define __clk_regmap_mux_hw(_p) __clk_regmap_hw(&(_p)->clkr) + +#define __CLK_REGMAP_MUX(_name, _parents, _ops, _flags, _ofs, _sft, _mask)= \ + struct clk_regmap_mux _name =3D { \ + .clkr.hw.init =3D \ + CLK_HW_INIT_PARENTS(#_name, _parents, _ops, _flags), \ + .mux_ofs =3D _ofs, \ + .shift =3D _sft, \ + .mask =3D _mask, \ + } + +#define CLK_REGMAP_MUX(_name, _parents, _flags, _ofs, _sft, _mask) = \ + __CLK_REGMAP_MUX(_name, _parents, &clk_regmap_mux_ops, _flags, _ofs, \ + _sft, _mask) + +static inline struct clk_regmap_mux *to_clk_regmap_mux(struct clk_hw *hw) +{ + struct clk_regmap *clkr =3D to_clk_regmap(hw); + + return container_of(clkr, struct clk_regmap_mux, clkr); +} + +extern const struct clk_ops clk_regmap_mux_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_MUX_H */ --=20 2.34.1