The RK3506 SoC introduces a secondary block-level pinmux controller called
RMIO (Rockchip Matrix I/O). When the primary IOMUX is selected to a
specific function, the pin signal is routed to the RMIO block, where a
secondary selection determines the final function.
This patch adds the necessary properties to support RMIO:
- rockchip,rmio: phandle to the RMIO syscon node.
- rockchip,rmio-pins: a matrix to configure the RMIO block.
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
---
.../bindings/pinctrl/rockchip,pinctrl.yaml | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
index 97960245676d..887bec22b172 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
@@ -66,6 +66,13 @@ properties:
Required for at least rk3188 and rk3288. On the rk3368 this should
point to the PMUGRF syscon.
+ rockchip,rmio:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The phandle of the syscon node for the RMIO registers, used by
+ some SoCs (e.g. rk3506) to configure the secondary block-level
+ pinmux functions.
+
"#address-cells":
enum: [1, 2]
@@ -144,6 +151,23 @@ additionalProperties:
The phandle of a node contains the generic pinconfig options
to use as described in pinctrl-bindings.txt.
+ rockchip,rmio-pins:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ items:
+ items:
+ - minimum: 0
+ description: RMIO ID (Controller index)
+ - minimum: 0
+ description: Pin index within the RMIO controller
+ - minimum: 0
+ description: Function Mux ID
+ description:
+ Configuration for the Rockchip Matrix I/O (RMIO) block. The format
+ is <rmio_id pin_id function_id>. This acts as a secondary muxing
+ layer when the primary 'rockchip,pins' mux is set to the RMIO
+ function.
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
--
2.34.1On Sat, Dec 27, 2025 at 12:55 PM Ye Zhang <ye.zhang@rock-chips.com> wrote: > + rockchip,rmio-pins: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + minItems: 1 > + items: > + items: > + - minimum: 0 > + description: RMIO ID (Controller index) > + - minimum: 0 > + description: Pin index within the RMIO controller > + - minimum: 0 > + description: Function Mux ID > + description: > + Configuration for the Rockchip Matrix I/O (RMIO) block. The format > + is <rmio_id pin_id function_id>. This acts as a secondary muxing > + layer when the primary 'rockchip,pins' mux is set to the RMIO > + function. I think this should just use the standard pinmux = <>; property with some shifting and masking. Yours, Linus Walleij
On Sat, Dec 27, 2025 at 07:49:55PM +0800, Ye Zhang wrote: > The RK3506 SoC introduces a secondary block-level pinmux controller called > RMIO (Rockchip Matrix I/O). When the primary IOMUX is selected to a > specific function, the pin signal is routed to the RMIO block, where a > secondary selection determines the final function. > > This patch adds the necessary properties to support RMIO: > - rockchip,rmio: phandle to the RMIO syscon node. > - rockchip,rmio-pins: a matrix to configure the RMIO block. > > Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com> > --- > .../bindings/pinctrl/rockchip,pinctrl.yaml | 24 +++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml > index 97960245676d..887bec22b172 100644 > --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml > @@ -66,6 +66,13 @@ properties: > Required for at least rk3188 and rk3288. On the rk3368 this should > point to the PMUGRF syscon. > > + rockchip,rmio: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + The phandle of the syscon node for the RMIO registers, used by > + some SoCs (e.g. rk3506) to configure the secondary block-level > + pinmux functions. > + You need to disallow it for other variants in if:then: block. > "#address-cells": > enum: [1, 2] > > @@ -144,6 +151,23 @@ additionalProperties: > The phandle of a node contains the generic pinconfig options > to use as described in pinctrl-bindings.txt. > > + rockchip,rmio-pins: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + minItems: 1 > + items: > + items: > + - minimum: 0 That's redundant. 0 is already minimum. > + description: RMIO ID (Controller index) Why do you need this? Is this pin controller having multiple RMIO IDs? Nothing like that was expressed in previous DTS. No other IDs are present in this DTS, either... > + - minimum: 0 > + description: Pin index within the RMIO controller > + - minimum: 0 > + description: Function Mux ID > + description: > + Configuration for the Rockchip Matrix I/O (RMIO) block. The format > + is <rmio_id pin_id function_id>. This acts as a secondary muxing > + layer when the primary 'rockchip,pins' mux is set to the RMIO > + function. > + > examples: > - | > #include <dt-bindings/interrupt-controller/arm-gic.h> > -- > 2.34.1 >
在 2025/12/28 18:37, Krzysztof Kozlowski 写道: > On Sat, Dec 27, 2025 at 07:49:55PM +0800, Ye Zhang wrote: >> The RK3506 SoC introduces a secondary block-level pinmux controller called >> RMIO (Rockchip Matrix I/O). When the primary IOMUX is selected to a >> specific function, the pin signal is routed to the RMIO block, where a >> secondary selection determines the final function. >> >> This patch adds the necessary properties to support RMIO: >> - rockchip,rmio: phandle to the RMIO syscon node. >> - rockchip,rmio-pins: a matrix to configure the RMIO block. >> >> Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com> >> --- >> .../bindings/pinctrl/rockchip,pinctrl.yaml | 24 +++++++++++++++++++ >> 1 file changed, 24 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml >> index 97960245676d..887bec22b172 100644 >> --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml >> +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml >> @@ -66,6 +66,13 @@ properties: >> Required for at least rk3188 and rk3288. On the rk3368 this should >> point to the PMUGRF syscon. >> >> + rockchip,rmio: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: >> + The phandle of the syscon node for the RMIO registers, used by >> + some SoCs (e.g. rk3506) to configure the secondary block-level >> + pinmux functions. >> + > You need to disallow it for other variants in if:then: block. Will be completed in v5. >> "#address-cells": >> enum: [1, 2] >> >> @@ -144,6 +151,23 @@ additionalProperties: >> The phandle of a node contains the generic pinconfig options >> to use as described in pinctrl-bindings.txt. >> >> + rockchip,rmio-pins: >> + $ref: /schemas/types.yaml#/definitions/uint32-matrix >> + minItems: 1 >> + items: >> + items: >> + - minimum: 0 > That's redundant. 0 is already minimum. I will remove it in v5 >> + description: RMIO ID (Controller index) > Why do you need this? Is this pin controller having multiple RMIO IDs? > Nothing like that was expressed in previous DTS. No other IDs are > present in this DTS, either... The RMIO hardware IP itself is designed to support multiple instances. Although the RK3506 only integrates one instance, other chips (like the RK2116) already utilize multiple RMIO blocks. We want to define the binding based on the capabilities of the IP block rather than the specific configuration of the RK3506. This ensures the binding format (3 cells) remains stable when support for multi-RMIO SoCs is added to Linux in the future, avoiding the need to handle different cell formats in the driver. We prefer to keep the ID column (fixed to 0 for RK3506) for this forward compatibility. Is this acceptable? >> + - minimum: 0 >> + description: Pin index within the RMIO controller >> + - minimum: 0 >> + description: Function Mux ID >> + description: >> + Configuration for the Rockchip Matrix I/O (RMIO) block. The format >> + is <rmio_id pin_id function_id>. This acts as a secondary muxing >> + layer when the primary 'rockchip,pins' mux is set to the RMIO >> + function. >> + >> examples: >> - | >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> -- >> 2.34.1 >> > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip >
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