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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2ebf64e08; Sat, 27 Dec 2025 19:50:05 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v4 5/7] dt-bindings: pinctrl: rockchip: Add rk3506 rmio support Date: Sat, 27 Dec 2025 19:49:55 +0800 Message-Id: <20251227114957.3287944-6-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251227114957.3287944-1-ye.zhang@rock-chips.com> References: <20251227114957.3287944-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9b5fa4f8a809d8kunm85cc97d2e30a64 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGUkdSVZPSUtOTkkYTRlPGRpWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=ZSdLH+ZcF3RZZpP6xKRbDNhs0yS9mWcg4tAQ72tlHCQusjor8NhauZTDceAmmwhg/lrY5c+Pm8fczb5xfxGzuKK2x2K/XFbVAAc3eXQtkbL5ZJLYBSz995RYwJLHClOvIZd0T5GWmcbyowINKfJ01iAV/TBcTZRCz25ZmFpYnIA=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=CUb3WvGCjbszmhGW+RQqN+i+i3u3FpqE02r/bmTKsh4=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" The RK3506 SoC introduces a secondary block-level pinmux controller called RMIO (Rockchip Matrix I/O). When the primary IOMUX is selected to a specific function, the pin signal is routed to the RMIO block, where a secondary selection determines the final function. This patch adds the necessary properties to support RMIO: - rockchip,rmio: phandle to the RMIO syscon node. - rockchip,rmio-pins: a matrix to configure the RMIO block. Signed-off-by: Ye Zhang --- .../bindings/pinctrl/rockchip,pinctrl.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yam= l b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 97960245676d..887bec22b172 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -66,6 +66,13 @@ properties: Required for at least rk3188 and rk3288. On the rk3368 this should point to the PMUGRF syscon. =20 + rockchip,rmio: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the RMIO registers, used by + some SoCs (e.g. rk3506) to configure the secondary block-level + pinmux functions. + "#address-cells": enum: [1, 2] =20 @@ -144,6 +151,23 @@ additionalProperties: The phandle of a node contains the generic pinconfig optio= ns to use as described in pinctrl-bindings.txt. =20 + rockchip,rmio-pins: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + items: + items: + - minimum: 0 + description: RMIO ID (Controller index) + - minimum: 0 + description: Pin index within the RMIO controller + - minimum: 0 + description: Function Mux ID + description: + Configuration for the Rockchip Matrix I/O (RMIO) block. The form= at + is . This acts as a secondary muxing + layer when the primary 'rockchip,pins' mux is set to the RMIO + function. + examples: - | #include --=20 2.34.1