From: Icenowy Zheng <uwu@icenowy.me>
Verisilicon has a series of display controllers prefixed with DC and
with self-identification facility like their GC series GPUs.
Add a device tree binding for it.
Depends on the specific DC model, it can have either one or two display
outputs, and each display output could be set to DPI signal or "DP"
signal (which seems to be some plain parallel bus to HDMI controllers).
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
Changes in v4:
- Added a comment for "verisilicon,dc" that says the ID/revision is
discoverable via registers.
- Removed clock minItems constraint w/o specific compatible strings.
Changes in v3:
- Added SoC-specific compatible string, and arm the binding with clock /
port checking for the specific SoC (with a 2-output DC).
Changes in v2:
- Fixed misspelt "versilicon" in title.
- Moved minItems in clock properties to be earlier than items.
- Re-aligned multi-line clocks and resets in example.
.../bindings/display/verisilicon,dc.yaml | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml
diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
new file mode 100644
index 0000000000000..fe64cc1466690
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Verisilicon DC-series display controllers
+
+maintainers:
+ - Icenowy Zheng <uwu@icenowy.me>
+
+properties:
+ $nodename:
+ pattern: "^display@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - thead,th1520-dc8200
+ - const: verisilicon,dc # DC IPs have discoverable ID/revision registers
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: DC Core clock
+ - description: DMA AXI bus clock
+ - description: Configuration AHB bus clock
+ - description: Pixel clock of output 0
+ - description: Pixel clock of output 1
+
+ clock-names:
+ items:
+ - const: core
+ - const: axi
+ - const: ahb
+ - const: pix0
+ - const: pix1
+
+ resets:
+ items:
+ - description: DC Core reset
+ - description: DMA AXI bus reset
+ - description: Configuration AHB bus reset
+
+ reset-names:
+ items:
+ - const: core
+ - const: axi
+ - const: ahb
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The first output channel , endpoint 0 should be
+ used for DPI format output and endpoint 1 should be used
+ for DP format output.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The second output channel if the DC variant
+ supports. Follow the same endpoint addressing rule with
+ the first port.
+
+ required:
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - ports
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: thead,th1520-dc8200
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ ports:
+ required:
+ - port@0
+ - port@1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/thead,th1520-clk-ap.h>
+ #include <dt-bindings/reset/thead,th1520-reset.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ display@ffef600000 {
+ compatible = "thead,th1520-dc8200", "verisilicon,dc";
+ reg = <0xff 0xef600000 0x0 0x100000>;
+ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_vo CLK_DPU_CCLK>,
+ <&clk_vo CLK_DPU_ACLK>,
+ <&clk_vo CLK_DPU_HCLK>,
+ <&clk_vo CLK_DPU_PIXELCLK0>,
+ <&clk_vo CLK_DPU_PIXELCLK1>;
+ clock-names = "core", "axi", "ahb", "pix0", "pix1";
+ resets = <&rst TH1520_RESET_ID_DPU_CORE>,
+ <&rst TH1520_RESET_ID_DPU_AXI>,
+ <&rst TH1520_RESET_ID_DPU_AHB>;
+ reset-names = "core", "axi", "ahb";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpu_out_dp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
+ };
--
2.52.0On Thu, Dec 25, 2025 at 12:11:58AM +0800, Icenowy Zheng wrote:
> From: Icenowy Zheng <uwu@icenowy.me>
>
> Verisilicon has a series of display controllers prefixed with DC and
> with self-identification facility like their GC series GPUs.
>
> Add a device tree binding for it.
>
> Depends on the specific DC model, it can have either one or two display
> outputs, and each display output could be set to DPI signal or "DP"
> signal (which seems to be some plain parallel bus to HDMI controllers).
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> ---
> Changes in v4:
> - Added a comment for "verisilicon,dc" that says the ID/revision is
> discoverable via registers.
> - Removed clock minItems constraint w/o specific compatible strings.
>
> Changes in v3:
> - Added SoC-specific compatible string, and arm the binding with clock /
> port checking for the specific SoC (with a 2-output DC).
>
> Changes in v2:
> - Fixed misspelt "versilicon" in title.
> - Moved minItems in clock properties to be earlier than items.
> - Re-aligned multi-line clocks and resets in example.
>
> .../bindings/display/verisilicon,dc.yaml | 144 ++++++++++++++++++
> 1 file changed, 144 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> new file mode 100644
> index 0000000000000..fe64cc1466690
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> @@ -0,0 +1,144 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Verisilicon DC-series display controllers
> +
> +maintainers:
> + - Icenowy Zheng <uwu@icenowy.me>
> +
> +properties:
> + $nodename:
> + pattern: "^display@[0-9a-f]+$"
> +
> + compatible:
> + items:
> + - enum:
> + - thead,th1520-dc8200
> + - const: verisilicon,dc # DC IPs have discoverable ID/revision registers
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: DC Core clock
> + - description: DMA AXI bus clock
> + - description: Configuration AHB bus clock
> + - description: Pixel clock of output 0
> + - description: Pixel clock of output 1
> +
> + clock-names:
> + items:
> + - const: core
> + - const: axi
> + - const: ahb
> + - const: pix0
> + - const: pix1
> +
> + resets:
> + items:
> + - description: DC Core reset
> + - description: DMA AXI bus reset
> + - description: Configuration AHB bus reset
> +
> + reset-names:
> + items:
> + - const: core
> + - const: axi
> + - const: ahb
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The first output channel , endpoint 0 should be
No space before comma. Or perhaps should be a period instead.
> + used for DPI format output and endpoint 1 should be used
> + for DP format output.
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The second output channel if the DC variant
> + supports. Follow the same endpoint addressing rule with
> + the first port.
> +
> + required:
> + - port@0
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - ports
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: thead,th1520-dc8200
> + then:
> + properties:
> + clocks:
> + minItems: 5
That's already implicitly the min. Perhaps you wanted 'minItems: 4' on
the clocks and clock-names definitions for versions with only 1 output?
> + ports:
> + required:
> + - port@0
> + - port@1
It is valid to omit these if the output is present, but unused.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/thead,th1520-clk-ap.h>
> + #include <dt-bindings/reset/thead,th1520-reset.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + display@ffef600000 {
> + compatible = "thead,th1520-dc8200", "verisilicon,dc";
> + reg = <0xff 0xef600000 0x0 0x100000>;
> + interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_vo CLK_DPU_CCLK>,
> + <&clk_vo CLK_DPU_ACLK>,
> + <&clk_vo CLK_DPU_HCLK>,
> + <&clk_vo CLK_DPU_PIXELCLK0>,
> + <&clk_vo CLK_DPU_PIXELCLK1>;
> + clock-names = "core", "axi", "ahb", "pix0", "pix1";
> + resets = <&rst TH1520_RESET_ID_DPU_CORE>,
> + <&rst TH1520_RESET_ID_DPU_AXI>,
> + <&rst TH1520_RESET_ID_DPU_AHB>;
> + reset-names = "core", "axi", "ahb";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dpu_out_dp1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&hdmi_in>;
> + };
> + };
> + };
> + };
> + };
> --
> 2.52.0
>
在 2026-01-05星期一的 09:46 -0600，Rob Herring写道： > On Thu, Dec 25, 2025 at 12:11:58AM +0800, Icenowy Zheng wrote: > > From: Icenowy Zheng <uwu@icenowy.me> > > > > Verisilicon has a series of display controllers prefixed with DC > > and > > with self-identification facility like their GC series GPUs. > > > > Add a device tree binding for it. > > > > Depends on the specific DC model, it can have either one or two > > display > > outputs, and each display output could be set to DPI signal or "DP" > > signal (which seems to be some plain parallel bus to HDMI > > controllers). > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> > > --- > > Changes in v4: > > - Added a comment for "verisilicon,dc" that says the ID/revision is > > discoverable via registers. > > - Removed clock minItems constraint w/o specific compatible > > strings. > > > > Changes in v3: > > - Added SoC-specific compatible string, and arm the binding with > > clock / > > port checking for the specific SoC (with a 2-output DC). > > > > Changes in v2: > > - Fixed misspelt "versilicon" in title. > > - Moved minItems in clock properties to be earlier than items. > > - Re-aligned multi-line clocks and resets in example. > > > > .../bindings/display/verisilicon,dc.yaml | 144 > > ++++++++++++++++++ > > 1 file changed, 144 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > new file mode 100644 > > index 0000000000000..fe64cc1466690 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > @@ -0,0 +1,144 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Verisilicon DC-series display controllers > > + > > +maintainers: > > + - Icenowy Zheng <uwu@icenowy.me> > > + > > +properties: > > + $nodename: > > + pattern: "^display@[0-9a-f]+$" > > + > > + compatible: > > + items: > > + - enum: > > + - thead,th1520-dc8200 > > + - const: verisilicon,dc # DC IPs have discoverable > > ID/revision registers > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: DC Core clock > > + - description: DMA AXI bus clock > > + - description: Configuration AHB bus clock > > + - description: Pixel clock of output 0 > > + - description: Pixel clock of output 1 > > + > > + clock-names: > > + items: > > + - const: core > > + - const: axi > > + - const: ahb > > + - const: pix0 > > + - const: pix1 > > + > > + resets: > > + items: > > + - description: DC Core reset > > + - description: DMA AXI bus reset > > + - description: Configuration AHB bus reset > > + > > + reset-names: > > + items: > > + - const: core > > + - const: axi > > + - const: ahb > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: The first output channel , endpoint 0 should > > be > > No space before comma. Or perhaps should be a period instead. Well I don't know why I inserted such a space, will remove it. > > > > + used for DPI format output and endpoint 1 should be used > > + for DP format output. > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: The second output channel if the DC variant > > + supports. Follow the same endpoint addressing rule with > > + the first port. > > + > > + required: > > + - port@0 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + - ports > > + > > +allOf: > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: thead,th1520-dc8200 > > + then: > > + properties: > > + clocks: > > + minItems: 5 > > That's already implicitly the min. Perhaps you wanted 'minItems: 4' > on > the clocks and clock-names definitions for versions with only 1 > output? Previously I specified minItems: 4 in the general part, however this does not play well when some of core/axi/ahb clocks are not present. > > > + ports: > > + required: > > + - port@0 > > + - port@1 > > It is valid to omit these if the output is present, but unused. Well this sounds reasonable, although my driver does not play well if only a port@1 is defined w/o port@0 . Considering the previous two snippets, should I just remove this if part? > > > + > > +additionalProperties: false > > + ====== 8< ========
On Mon, Jan 5, 2026 at 10:13 AM Icenowy Zheng <uwu@icenowy.me> wrote: > > 在 2026-01-05星期一的 09:46 -0600，Rob Herring写道： > > On Thu, Dec 25, 2025 at 12:11:58AM +0800, Icenowy Zheng wrote: > > > From: Icenowy Zheng <uwu@icenowy.me> > > > > > > Verisilicon has a series of display controllers prefixed with DC > > > and > > > with self-identification facility like their GC series GPUs. > > > > > > Add a device tree binding for it. > > > > > > Depends on the specific DC model, it can have either one or two > > > display > > > outputs, and each display output could be set to DPI signal or "DP" > > > signal (which seems to be some plain parallel bus to HDMI > > > controllers). > > > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> > > > --- > > > Changes in v4: > > > - Added a comment for "verisilicon,dc" that says the ID/revision is > > > discoverable via registers. > > > - Removed clock minItems constraint w/o specific compatible > > > strings. > > > > > > Changes in v3: > > > - Added SoC-specific compatible string, and arm the binding with > > > clock / > > > port checking for the specific SoC (with a 2-output DC). > > > > > > Changes in v2: > > > - Fixed misspelt "versilicon" in title. > > > - Moved minItems in clock properties to be earlier than items. > > > - Re-aligned multi-line clocks and resets in example. > > > > > > .../bindings/display/verisilicon,dc.yaml | 144 > > > ++++++++++++++++++ > > > 1 file changed, 144 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > new file mode 100644 > > > index 0000000000000..fe64cc1466690 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > @@ -0,0 +1,144 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Verisilicon DC-series display controllers > > > + > > > +maintainers: > > > + - Icenowy Zheng <uwu@icenowy.me> > > > + > > > +properties: > > > + $nodename: > > > + pattern: "^display@[0-9a-f]+$" > > > + > > > + compatible: > > > + items: > > > + - enum: > > > + - thead,th1520-dc8200 > > > + - const: verisilicon,dc # DC IPs have discoverable > > > ID/revision registers > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + clocks: > > > + items: > > > + - description: DC Core clock > > > + - description: DMA AXI bus clock > > > + - description: Configuration AHB bus clock > > > + - description: Pixel clock of output 0 > > > + - description: Pixel clock of output 1 > > > + > > > + clock-names: > > > + items: > > > + - const: core > > > + - const: axi > > > + - const: ahb > > > + - const: pix0 > > > + - const: pix1 > > > + > > > + resets: > > > + items: > > > + - description: DC Core reset > > > + - description: DMA AXI bus reset > > > + - description: Configuration AHB bus reset > > > + > > > + reset-names: > > > + items: > > > + - const: core > > > + - const: axi > > > + - const: ahb > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: The first output channel , endpoint 0 should > > > be > > > > No space before comma. Or perhaps should be a period instead. > > Well I don't know why I inserted such a space, will remove it. > > > > > > > > + used for DPI format output and endpoint 1 should be used > > > + for DP format output. > > > + > > > + port@1: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: The second output channel if the DC variant > > > + supports. Follow the same endpoint addressing rule with > > > + the first port. > > > + > > > + required: > > > + - port@0 > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + - clocks > > > + - clock-names > > > + - ports > > > + > > > +allOf: > > > + - if: > > > + properties: > > > + compatible: > > > + contains: > > > + const: thead,th1520-dc8200 > > > + then: > > > + properties: > > > + clocks: > > > + minItems: 5 > > > > That's already implicitly the min. Perhaps you wanted 'minItems: 4' > > on > > the clocks and clock-names definitions for versions with only 1 > > output? > > Previously I specified minItems: 4 in the general part, however this > does not play well when some of core/axi/ahb clocks are not present. I don't understand. That would only make pix1 optional. There of course is no way we can check that 'clocks' entries are pointing to the correct clocks. > > > + ports: > > > + required: > > > + - port@0 > > > + - port@1 > > > > It is valid to omit these if the output is present, but unused. > > Well this sounds reasonable, although my driver does not play well if > only a port@1 is defined w/o port@0 . Sounds like your driver should be fixed. > Considering the previous two snippets, should I just remove this if > part? I would, yes. Rob
在 2026-01-05星期一的 10:20 -0600，Rob Herring写道： ========== 8< ============== > > > > + ports: > > > > + required: > > > > + - port@0 > > > > + - port@1 > > > > > > It is valid to omit these if the output is present, but unused. > > > > Well this sounds reasonable, although my driver does not play well > > if > > only a port@1 is defined w/o port@0 . > > Sounds like your driver should be fixed. After this requirement is dropped, should the unconnected port@0 also be removed from the DT example? > > > Considering the previous two snippets, should I just remove this if > > part? > > I would, yes. > > Rob
> On Dec 25, 2025, at 00:11, Icenowy Zheng <zhengxingda@iscas.ac.cn> wrote:
>
> From: Icenowy Zheng <uwu@icenowy.me>
>
> Verisilicon has a series of display controllers prefixed with DC and
> with self-identification facility like their GC series GPUs.
>
> Add a device tree binding for it.
>
> Depends on the specific DC model, it can have either one or two display
> outputs, and each display output could be set to DPI signal or "DP"
> signal (which seems to be some plain parallel bus to HDMI controllers).
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> ---
> Changes in v4:
> - Added a comment for "verisilicon,dc" that says the ID/revision is
> discoverable via registers.
> - Removed clock minItems constraint w/o specific compatible strings.
>
> Changes in v3:
> - Added SoC-specific compatible string, and arm the binding with clock /
> port checking for the specific SoC (with a 2-output DC).
>
> Changes in v2:
> - Fixed misspelt "versilicon" in title.
> - Moved minItems in clock properties to be earlier than items.
> - Re-aligned multi-line clocks and resets in example.
>
> .../bindings/display/verisilicon,dc.yaml | 144 ++++++++++++++++++
> 1 file changed, 144 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> new file mode 100644
> index 0000000000000..fe64cc1466690
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> @@ -0,0 +1,144 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Verisilicon DC-series display controllers
> +
> +maintainers:
> + - Icenowy Zheng <uwu@icenowy.me>
> +
> +properties:
> + $nodename:
> + pattern: "^display@[0-9a-f]+$"
> +
> + compatible:
> + items:
> + - enum:
> + - thead,th1520-dc8200
> + - const: verisilicon,dc # DC IPs have discoverable ID/revision registers
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: DC Core clock
> + - description: DMA AXI bus clock
> + - description: Configuration AHB bus clock
> + - description: Pixel clock of output 0
> + - description: Pixel clock of output 1
> +
> + clock-names:
> + items:
> + - const: core
> + - const: axi
> + - const: ahb
> + - const: pix0
> + - const: pix1
> +
> + resets:
> + items:
> + - description: DC Core reset
> + - description: DMA AXI bus reset
> + - description: Configuration AHB bus reset
> +
> + reset-names:
> + items:
> + - const: core
> + - const: axi
> + - const: ahb
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The first output channel , endpoint 0 should be
> + used for DPI format output and endpoint 1 should be used
> + for DP format output.
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The second output channel if the DC variant
> + supports. Follow the same endpoint addressing rule with
> + the first port.
> +
> + required:
> + - port@0
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - ports
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: thead,th1520-dc8200
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + ports:
> + required:
> + - port@0
> + - port@1
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/thead,th1520-clk-ap.h>
> + #include <dt-bindings/reset/thead,th1520-reset.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + display@ffef600000 {
> + compatible = "thead,th1520-dc8200", "verisilicon,dc";
> + reg = <0xff 0xef600000 0x0 0x100000>;
> + interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_vo CLK_DPU_CCLK>,
> + <&clk_vo CLK_DPU_ACLK>,
> + <&clk_vo CLK_DPU_HCLK>,
> + <&clk_vo CLK_DPU_PIXELCLK0>,
> + <&clk_vo CLK_DPU_PIXELCLK1>;
> + clock-names = "core", "axi", "ahb", "pix0", "pix1";
> + resets = <&rst TH1520_RESET_ID_DPU_CORE>,
> + <&rst TH1520_RESET_ID_DPU_AXI>,
> + <&rst TH1520_RESET_ID_DPU_AHB>;
> + reset-names = "core", "axi", "ahb";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dpu_out_dp1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&hdmi_in>;
> + };
> + };
> + };
> + };
> + };
> --
> 2.52.0
>
Tested-by: Han Gao <gaohan@iscas.ac.cn <mailto:gaohan@iscas.ac.cn>>
On Thu, Dec 25, 2025 at 05:35:34PM +0800, Han Gao (Revy) wrote:
> +
> > + dpu_out_dp1: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&hdmi_in>;
> > + };
> > + };
> > + };
> > + };
> > + };
> > --
> > 2.52.0
> >
> Tested-by: Han Gao <gaohan@iscas.ac.cn <mailto:gaohan@iscas.ac.cn>>
No, really, how?
Please explain me how can you test a binding (and build process is not
testing, otherwise we all should keep getting tested-by, especially
Rob!)
I don't agree on fake tags.
> On Dec 25, 2025, at 00:11, Icenowy Zheng <zhengxingda@iscas.ac.cn> wrote:
>
> From: Icenowy Zheng <uwu@icenowy.me>
>
> Verisilicon has a series of display controllers prefixed with DC and
> with self-identification facility like their GC series GPUs.
>
> Add a device tree binding for it.
>
> Depends on the specific DC model, it can have either one or two display
> outputs, and each display output could be set to DPI signal or "DP"
> signal (which seems to be some plain parallel bus to HDMI controllers).
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> ---
> Changes in v4:
> - Added a comment for "verisilicon,dc" that says the ID/revision is
> discoverable via registers.
> - Removed clock minItems constraint w/o specific compatible strings.
>
> Changes in v3:
> - Added SoC-specific compatible string, and arm the binding with clock /
> port checking for the specific SoC (with a 2-output DC).
>
> Changes in v2:
> - Fixed misspelt "versilicon" in title.
> - Moved minItems in clock properties to be earlier than items.
> - Re-aligned multi-line clocks and resets in example.
>
> .../bindings/display/verisilicon,dc.yaml | 144 ++++++++++++++++++
> 1 file changed, 144 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> new file mode 100644
> index 0000000000000..fe64cc1466690
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> @@ -0,0 +1,144 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Verisilicon DC-series display controllers
> +
> +maintainers:
> + - Icenowy Zheng <uwu@icenowy.me>
> +
> +properties:
> + $nodename:
> + pattern: "^display@[0-9a-f]+$"
> +
> + compatible:
> + items:
> + - enum:
> + - thead,th1520-dc8200
> + - const: verisilicon,dc # DC IPs have discoverable ID/revision registers
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: DC Core clock
> + - description: DMA AXI bus clock
> + - description: Configuration AHB bus clock
> + - description: Pixel clock of output 0
> + - description: Pixel clock of output 1
> +
> + clock-names:
> + items:
> + - const: core
> + - const: axi
> + - const: ahb
> + - const: pix0
> + - const: pix1
> +
> + resets:
> + items:
> + - description: DC Core reset
> + - description: DMA AXI bus reset
> + - description: Configuration AHB bus reset
> +
> + reset-names:
> + items:
> + - const: core
> + - const: axi
> + - const: ahb
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The first output channel , endpoint 0 should be
> + used for DPI format output and endpoint 1 should be used
> + for DP format output.
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The second output channel if the DC variant
> + supports. Follow the same endpoint addressing rule with
> + the first port.
> +
> + required:
> + - port@0
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - ports
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: thead,th1520-dc8200
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + ports:
> + required:
> + - port@0
> + - port@1
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/thead,th1520-clk-ap.h>
> + #include <dt-bindings/reset/thead,th1520-reset.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + display@ffef600000 {
> + compatible = "thead,th1520-dc8200", "verisilicon,dc";
> + reg = <0xff 0xef600000 0x0 0x100000>;
> + interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_vo CLK_DPU_CCLK>,
> + <&clk_vo CLK_DPU_ACLK>,
> + <&clk_vo CLK_DPU_HCLK>,
> + <&clk_vo CLK_DPU_PIXELCLK0>,
> + <&clk_vo CLK_DPU_PIXELCLK1>;
> + clock-names = "core", "axi", "ahb", "pix0", "pix1";
> + resets = <&rst TH1520_RESET_ID_DPU_CORE>,
> + <&rst TH1520_RESET_ID_DPU_AXI>,
> + <&rst TH1520_RESET_ID_DPU_AHB>;
> + reset-names = "core", "axi", "ahb";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dpu_out_dp1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&hdmi_in>;
> + };
> + };
> + };
> + };
> + };
> --
> 2.52.0
>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
On Thu, Dec 25, 2025 at 05:45:00PM +0800, Han Gao (Revy) wrote:
> > + dpu_out_dp1: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&hdmi_in>;
> > + };
> > + };
> > + };
> > + };
> > + };
> > --
> > 2.52.0
> >
>
> Tested-by: Han Gao <gaohan@iscas.ac.cn>
NAK, not true. Otherwise explain me how can you test the bindings.
On Sat, Dec 27, 2025 at 7:09 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Thu, Dec 25, 2025 at 05:45:00PM +0800, Han Gao (Revy) wrote:
> > > + dpu_out_dp1: endpoint@1 {
> > > + reg = <1>;
> > > + remote-endpoint = <&hdmi_in>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > + };
> > > --
> > > 2.52.0
> > >
> >
> > Tested-by: Han Gao <gaohan@iscas.ac.cn>
>
> NAK, not true. Otherwise explain me how can you test the bindings.
>
>
I cherry-picked the patches I gave to Tested-by on my test branch,
compiled and ran them on Lichee Pi 4a.
All the relevant patches were also given to Tested-by.
On 27/12/2025 13:08, Han Gao wrote:
> On Sat, Dec 27, 2025 at 7:09 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On Thu, Dec 25, 2025 at 05:45:00PM +0800, Han Gao (Revy) wrote:
>>>> + dpu_out_dp1: endpoint@1 {
>>>> + reg = <1>;
>>>> + remote-endpoint = <&hdmi_in>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> --
>>>> 2.52.0
>>>>
>>>
>>> Tested-by: Han Gao <gaohan@iscas.ac.cn>
>>
>> NAK, not true. Otherwise explain me how can you test the bindings.
>>
>>
> I cherry-picked the patches I gave to Tested-by on my test branch,
> compiled and ran them on Lichee Pi 4a.
You cannot "run a binding".
Best regards,
Krzysztof
On Sun, Dec 28, 2025 at 3:49 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 27/12/2025 13:08, Han Gao wrote:
> > On Sat, Dec 27, 2025 at 7:09 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>
> >> On Thu, Dec 25, 2025 at 05:45:00PM +0800, Han Gao (Revy) wrote:
> >>>> + dpu_out_dp1: endpoint@1 {
> >>>> + reg = <1>;
> >>>> + remote-endpoint = <&hdmi_in>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> --
> >>>> 2.52.0
> >>>>
> >>>
> >>> Tested-by: Han Gao <gaohan@iscas.ac.cn>
> >>
> >> NAK, not true. Otherwise explain me how can you test the bindings.
> >>
> >>
> > I cherry-picked the patches I gave to Tested-by on my test branch,
> > compiled and ran them on Lichee Pi 4a.
>
> You cannot "run a binding".
I understand now. My understanding of dt-binding testing was incorrect.
I will not repeat this mistake in Tested-By.
>
>
>
> Best regards,
> Krzysztof
© 2016 - 2026 Red Hat, Inc.