From nobody Tue Feb 10 14:32:17 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E190248F5C; Wed, 24 Dec 2025 16:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766592787; cv=none; b=dB0PlvIfqLbxYfdFROmW1VpJJJ4x3Dp0ruGBWpzOhcHyTDDq+drtbHx/N5ttFx0dE34NMisdxNXNAfFdpx63q18Eqm6EyCUnOu2qSRE3fvph4CwgqrwRxLlMF9hxBKrd/LSyJ8IVNO+XPMRe9o0j81pxaodTE0eVgnzzBFEE8X4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766592787; c=relaxed/simple; bh=LZQOeRubQXaFADHp4W7ZbqlSE20vrG5kwc9CRgIjIgQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CW+5s48dzNruk1jIncPjpq8ZAo3uKEvnJuo6VBTGDh593AewFr1lbIeLjnk49BRqhnptXbijoQsepC//B8N2N6nYhoVAfVD7Bg1o/9BfgUHLEbiCoIbCP7q6v39aOV5gqXBTiDjKypDUeb91OIUm25PrEvWgDNvoOQmLlaZASf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.54]) by APP-05 (Coremail) with SMTP id zQCowAA3yw7WEExpgGPNAQ--.14041S4; Thu, 25 Dec 2025 00:12:14 +0800 (CST) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Icenowy Zheng Subject: [PATCH v4 2/9] dt-bindings: display: add verisilicon,dc Date: Thu, 25 Dec 2025 00:11:58 +0800 Message-ID: <20251224161205.1132149-3-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224161205.1132149-1-zhengxingda@iscas.ac.cn> References: <20251224161205.1132149-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAA3yw7WEExpgGPNAQ--.14041S4 X-Coremail-Antispam: 1UD129KBjvJXoWxur17uw4ftr1DtFWrKr15Jwb_yoWrur1Dpa n3AFW8tF4vqF13Xws3JFyIgw4rKan5ZF10gryxX34jyan0gF10qw4akr98ZasrJF92vay7 WFWj9r4Ik3WI9aUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmY14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r4UJwAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUXVWUAwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67 kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY 6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42 IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIev Ja73UjIFyTuYvjTR_3kZDUUUU X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" From: Icenowy Zheng Verisilicon has a series of display controllers prefixed with DC and with self-identification facility like their GC series GPUs. Add a device tree binding for it. Depends on the specific DC model, it can have either one or two display outputs, and each display output could be set to DPI signal or "DP" signal (which seems to be some plain parallel bus to HDMI controllers). Signed-off-by: Icenowy Zheng Signed-off-by: Icenowy Zheng Tested-by: Han Gao > Tested-by: Han Gao --- Changes in v4: - Added a comment for "verisilicon,dc" that says the ID/revision is discoverable via registers. - Removed clock minItems constraint w/o specific compatible strings. Changes in v3: - Added SoC-specific compatible string, and arm the binding with clock / port checking for the specific SoC (with a 2-output DC). Changes in v2: - Fixed misspelt "versilicon" in title. - Moved minItems in clock properties to be earlier than items. - Re-aligned multi-line clocks and resets in example. .../bindings/display/verisilicon,dc.yaml | 144 ++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/verisilicon,d= c.yaml diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml = b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml new file mode 100644 index 0000000000000..fe64cc1466690 --- /dev/null +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Verisilicon DC-series display controllers + +maintainers: + - Icenowy Zheng + +properties: + $nodename: + pattern: "^display@[0-9a-f]+$" + + compatible: + items: + - enum: + - thead,th1520-dc8200 + - const: verisilicon,dc # DC IPs have discoverable ID/revision regis= ters + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DC Core clock + - description: DMA AXI bus clock + - description: Configuration AHB bus clock + - description: Pixel clock of output 0 + - description: Pixel clock of output 1 + + clock-names: + items: + - const: core + - const: axi + - const: ahb + - const: pix0 + - const: pix1 + + resets: + items: + - description: DC Core reset + - description: DMA AXI bus reset + - description: Configuration AHB bus reset + + reset-names: + items: + - const: core + - const: axi + - const: ahb + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The first output channel , endpoint 0 should be + used for DPI format output and endpoint 1 should be used + for DP format output. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The second output channel if the DC variant + supports. Follow the same endpoint addressing rule with + the first port. + + required: + - port@0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: thead,th1520-dc8200 + then: + properties: + clocks: + minItems: 5 + ports: + required: + - port@0 + - port@1 + +additionalProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + display@ffef600000 { + compatible =3D "thead,th1520-dc8200", "verisilicon,dc"; + reg =3D <0xff 0xef600000 0x0 0x100000>; + interrupts =3D <93 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_DPU_CCLK>, + <&clk_vo CLK_DPU_ACLK>, + <&clk_vo CLK_DPU_HCLK>, + <&clk_vo CLK_DPU_PIXELCLK0>, + <&clk_vo CLK_DPU_PIXELCLK1>; + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; + resets =3D <&rst TH1520_RESET_ID_DPU_CORE>, + <&rst TH1520_RESET_ID_DPU_AXI>, + <&rst TH1520_RESET_ID_DPU_AHB>; + reset-names =3D "core", "axi", "ahb"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_out_dp1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&hdmi_in>; + }; + }; + }; + }; + }; --=20 2.52.0