From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add support for device_{pause, resume}() callbacks. These are required by
the RZ/G2L SCIFA driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v5:
- used suspend capability of the controller to pause/resume
  the transfers

 drivers/dma/sh/rz-dmac.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
index c3035b94ef2c..e349ade1845f 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -135,6 +135,7 @@ struct rz_dmac {
 #define CHANNEL_8_15_COMMON_BASE	0x0700
 
 #define CHSTAT_ER			BIT(4)
+#define CHSTAT_SUS			BIT(3)
 #define CHSTAT_EN			BIT(0)
 
 #define CHCTRL_CLRINTMSK		BIT(17)
@@ -827,6 +828,38 @@ static enum dma_status rz_dmac_tx_status(struct dma_chan *chan,
 	return status;
 }
 
+static int rz_dmac_device_pause(struct dma_chan *chan)
+{
+	struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
+	u32 val;
+
+	scoped_guard(spinlock_irqsave, &channel->vc.lock) {
+		val = rz_dmac_ch_readl(channel, CHCTRL, 1);
+		val |= CHCTRL_CLRSUS;
+		rz_dmac_ch_writel(channel, val, CHCTRL, 1);
+	}
+
+	return read_poll_timeout_atomic(rz_dmac_ch_readl, val,
+					(val & CHSTAT_SUS), 1, 1024, false,
+					channel, CHSTAT, 1);
+}
+
+static int rz_dmac_device_resume(struct dma_chan *chan)
+{
+	struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
+	u32 val;
+
+	scoped_guard(spinlock_irqsave, &channel->vc.lock) {
+		val = rz_dmac_ch_readl(channel, CHCTRL, 1);
+		val &= ~CHCTRL_CLRSUS;
+		rz_dmac_ch_writel(channel, val, CHCTRL, 1);
+	}
+
+	return read_poll_timeout_atomic(rz_dmac_ch_readl, val,
+					!(val & CHSTAT_SUS), 1, 1024, false,
+					channel, CHSTAT, 1);
+}
+
 /*
  * -----------------------------------------------------------------------------
  * IRQ handling
@@ -1164,6 +1197,8 @@ static int rz_dmac_probe(struct platform_device *pdev)
 	engine->device_terminate_all = rz_dmac_terminate_all;
 	engine->device_issue_pending = rz_dmac_issue_pending;
 	engine->device_synchronize = rz_dmac_device_synchronize;
+	engine->device_pause = rz_dmac_device_pause;
+	engine->device_resume = rz_dmac_device_resume;
 
 	engine->copy_align = DMAENGINE_ALIGN_1_BYTE;
 	dma_set_max_seg_size(engine->dev, U32_MAX);
-- 
2.43.0

Hi,

On 12/17/25 15:52, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Add support for device_{pause, resume}() callbacks. These are required by
> the RZ/G2L SCIFA driver.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> 
> Changes in v5:
> - used suspend capability of the controller to pause/resume
>    the transfers
> 
>   drivers/dma/sh/rz-dmac.c | 35 +++++++++++++++++++++++++++++++++++
>   1 file changed, 35 insertions(+)
> 
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> index c3035b94ef2c..e349ade1845f 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -135,6 +135,7 @@ struct rz_dmac {
>   #define CHANNEL_8_15_COMMON_BASE	0x0700
>   
>   #define CHSTAT_ER			BIT(4)
> +#define CHSTAT_SUS			BIT(3)
>   #define CHSTAT_EN			BIT(0)
>   
>   #define CHCTRL_CLRINTMSK		BIT(17)
> @@ -827,6 +828,38 @@ static enum dma_status rz_dmac_tx_status(struct dma_chan *chan,
>   	return status;
>   }
>   
> +static int rz_dmac_device_pause(struct dma_chan *chan)
> +{
> +	struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
> +	u32 val;
> +
> +	scoped_guard(spinlock_irqsave, &channel->vc.lock) {
> +		val = rz_dmac_ch_readl(channel, CHCTRL, 1);
> +		val |= CHCTRL_CLRSUS;

This is wrong, I overlooked it. It should have set the CHCTRL_SETSUS bit.

> +		rz_dmac_ch_writel(channel, val, CHCTRL, 1);
> +	}
> +
> +	return read_poll_timeout_atomic(rz_dmac_ch_readl, val,
> +					(val & CHSTAT_SUS), 1, 1024, false,
> +					channel, CHSTAT, 1);
> +}
> +
> +static int rz_dmac_device_resume(struct dma_chan *chan)
> +{
> +	struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
> +	u32 val;
> +
> +	scoped_guard(spinlock_irqsave, &channel->vc.lock) {
> +		val = rz_dmac_ch_readl(channel, CHCTRL, 1);
> +		val &= ~CHCTRL_CLRSUS;

Same here. It should have set the CHCTRL_CLRSUS bit.

I'll update it in the next version.

Thank you,
Claudiu