From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
DPU version 13.0.0 introduces structural changes including
register additions, removals, and relocations.
Refactor SSPP-related code to be compatible with DPU 13.0.0
modifications.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 15 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 155 ++++++++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 ++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
6 files changed, 191 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 0eb7cdf82ff9..f2aba9bdfcd3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -208,6 +208,18 @@ struct dpu_dsc_blk {
u32 len;
};
+/**
+ * struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information
+ * @name: string name for debug purposes
+ * @base: offset of this sub-block relative to the block offset
+ * @len: register block length of this sub-block
+ */
+struct dpu_sspp_v13_rec_blk {
+ char name[DPU_HW_BLK_NAME_LEN];
+ u32 base;
+ u32 len;
+};
+
/**
* enum dpu_qos_lut_usage - define QoS LUT use cases
*/
@@ -294,7 +306,8 @@ struct dpu_sspp_sub_blks {
u32 qseed_ver;
struct dpu_scaler_blk scaler_blk;
struct dpu_pp_blk csc_blk;
-
+ struct dpu_sspp_v13_rec_blk sspp_rec0_blk;
+ struct dpu_sspp_v13_rec_blk sspp_rec1_blk;
const u32 *format_list;
u32 num_formats;
const struct dpu_rotation_cfg *rotation_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 6f1fc790ad6d..7ed28009c463 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -145,11 +145,18 @@
static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- u32 mode_mask;
if (!ctx)
return;
+ dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE);
+}
+
+void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_sspp *ctx, u32 op_mode_off)
+{
+ u32 mode_mask;
+
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
/**
* if rect index is RECT_SOLO, we cannot expect a
@@ -158,7 +165,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
*/
mode_mask = 0;
} else {
- mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE);
+ mode_mask = DPU_REG_READ(&ctx->hw, op_mode_off);
mode_mask |= pipe->multirect_index;
if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
mode_mask |= BIT(2);
@@ -166,11 +173,11 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
mode_mask &= ~BIT(2);
}
- DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask);
+ DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask);
}
-static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
- u32 mask, u8 en)
+void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
+ u32 mask, u8 en)
{
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
u32 opmode;
@@ -189,8 +196,8 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);
}
-static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
- u32 mask, u8 en)
+void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
+ u32 mask, u8 en)
{
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
u32 opmode;
@@ -211,10 +218,6 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
const struct msm_format *fmt, u32 flags)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- struct dpu_hw_blk_reg_map *c;
- u32 chroma_samp, unpack, src_format;
- u32 opmode = 0;
- u32 fast_clear = 0;
u32 op_mode_off, unpack_pat_off, format_off;
if (!ctx || !fmt)
@@ -231,7 +234,25 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
format_off = SSPP_SRC_FORMAT_REC1;
}
+ dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
+ unpack_pat_off, format_off,
+ SSPP_UBWC_STATIC_CTRL, SSPP_UBWC_ERROR_STATUS);
+}
+
+void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
+ u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off,
+ u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off,
+ u32 ubwc_err_off)
+{
+ struct dpu_hw_blk_reg_map *c;
+ u32 chroma_samp, unpack, src_format;
+ u32 opmode;
+ u32 fast_clear;
+ u8 core_major_ver;
+
c = &ctx->hw;
+ core_major_ver = ctx->mdss_ver->core_major_ver;
+
opmode = DPU_REG_READ(c, op_mode_off);
opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
@@ -273,31 +294,34 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
if (MSM_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
- DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
- DPU_FETCH_CONFIG_RESET_VALUE |
- ctx->ubwc->highest_bank_bit << 18);
+
+ if (core_major_ver < 13)
+ DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
+ DPU_FETCH_CONFIG_RESET_VALUE |
+ ctx->ubwc->highest_bank_bit << 18);
+
switch (ctx->ubwc->ubwc_enc_version) {
case UBWC_1_0:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
- fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
- BIT(8) |
- (ctx->ubwc->highest_bank_bit << 4));
+ DPU_REG_WRITE(c, ubwc_ctrl_off,
+ fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
+ BIT(8) |
+ (ctx->ubwc->highest_bank_bit << 4));
break;
case UBWC_2_0:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
- fast_clear | (ctx->ubwc->ubwc_swizzle) |
- (ctx->ubwc->highest_bank_bit << 4));
+ DPU_REG_WRITE(c, ubwc_ctrl_off,
+ fast_clear | (ctx->ubwc->ubwc_swizzle) |
+ (ctx->ubwc->highest_bank_bit << 4));
break;
case UBWC_3_0:
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
- BIT(30) | (ctx->ubwc->ubwc_swizzle) |
- (ctx->ubwc->highest_bank_bit << 4));
+ DPU_REG_WRITE(c, ubwc_ctrl_off,
+ BIT(30) | (ctx->ubwc->ubwc_swizzle) |
+ (ctx->ubwc->highest_bank_bit << 4));
break;
case UBWC_4_0:
- DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
- MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
+ DPU_REG_WRITE(c, ubwc_ctrl_off,
+ MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
break;
}
}
@@ -313,19 +337,18 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
/* update scaler opmode, if appropriate */
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
- _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
- MSM_FORMAT_IS_YUV(fmt));
+ dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
+ MSM_FORMAT_IS_YUV(fmt));
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
- _sspp_setup_csc10_opmode(ctx,
- VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
- MSM_FORMAT_IS_YUV(fmt));
+ dpu_hw_sspp_setup_csc10_opmode(ctx,
+ VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
+ MSM_FORMAT_IS_YUV(fmt));
DPU_REG_WRITE(c, format_off, src_format);
DPU_REG_WRITE(c, unpack_pat_off, unpack);
DPU_REG_WRITE(c, op_mode_off, opmode);
-
/* clear previous UBWC error */
- DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
+ DPU_REG_WRITE(c, ubwc_err_off, BIT(31));
}
static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
@@ -385,9 +408,9 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
tot_req_pixels[3]);
}
-static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
- struct dpu_hw_scaler3_cfg *scaler3_cfg,
- const struct msm_format *format)
+void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
+ struct dpu_hw_scaler3_cfg *scaler3_cfg,
+ const struct msm_format *format)
{
if (!ctx || !scaler3_cfg)
return;
@@ -405,15 +428,11 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *cfg)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- struct dpu_hw_blk_reg_map *c;
- u32 src_size, src_xy, dst_size, dst_xy;
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
if (!ctx || !cfg)
return;
- c = &ctx->hw;
-
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
pipe->multirect_index == DPU_SSPP_RECT_0) {
src_size_off = SSPP_SRC_SIZE;
@@ -427,20 +446,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
out_xy_off = SSPP_OUT_XY_REC1;
}
-
- /* src and dest rect programming */
- src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
- src_size = (drm_rect_height(&cfg->src_rect) << 16) |
- drm_rect_width(&cfg->src_rect);
- dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
- dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
- drm_rect_width(&cfg->dst_rect);
-
- /* rectangle register programming */
- DPU_REG_WRITE(c, src_size_off, src_size);
- DPU_REG_WRITE(c, src_xy_off, src_xy);
- DPU_REG_WRITE(c, out_size_off, dst_size);
- DPU_REG_WRITE(c, out_xy_off, dst_xy);
+ dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
+ src_xy_off, out_size_off, out_xy_off);
}
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
@@ -497,8 +504,8 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);
}
-static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
- const struct dpu_csc_cfg *data)
+void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
+ const struct dpu_csc_cfg *data)
{
u32 offset;
bool csc10 = false;
@@ -519,21 +526,31 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- struct dpu_hw_fmt_layout cfg;
+ u32 const_clr_off;
if (!ctx)
return;
+ if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
+ pipe->multirect_index == DPU_SSPP_RECT_0)
+ const_clr_off = SSPP_SRC_CONSTANT_COLOR;
+ else
+ const_clr_off = SSPP_SRC_CONSTANT_COLOR_REC1;
+
+ dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
+}
+
+void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
+ u32 color, struct dpu_hw_sspp *ctx,
+ u32 const_clr_off)
+{
+ struct dpu_hw_fmt_layout cfg;
+
/* cleanup source addresses */
memset(&cfg, 0, sizeof(cfg));
ctx->ops.setup_sourceaddress(pipe, &cfg);
- if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
- pipe->multirect_index == DPU_SSPP_RECT_0)
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color);
- else
- DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1,
- color);
+ DPU_REG_WRITE(&ctx->hw, const_clr_off, color);
}
static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
@@ -547,14 +564,20 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
cfg);
}
+void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
+ bool danger_safe_en, u32 ctrl_off)
+{
+ DPU_REG_WRITE(&ctx->hw, ctrl_off,
+ danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
+}
+
static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
bool danger_safe_en)
{
if (!ctx)
return;
- DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
- danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
+ dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL);
}
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
@@ -609,7 +632,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c,
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
- c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
+ c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
if (test_bit(DPU_SSPP_CDP, &features))
c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index bdac5c04bf79..c6b19cb4d158 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -331,5 +331,57 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
struct dentry *entry);
+void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
+ u32 mask, u8 en);
+
+void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
+ u32 mask, u8 en);
+
+void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
+ struct dpu_hw_scaler3_cfg *scaler3_cfg,
+ const struct msm_format *format);
+
+void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
+ const struct dpu_csc_cfg *data);
+
+void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
+ struct dpu_hw_sspp *ctx,
+ u32 op_mode_off);
+
+void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
+ u32 flags, struct dpu_hw_sspp *ctx,
+ u32 op_mode_off, u32 unpack_pat_off, u32 format_off,
+ u32 ubwc_ctrl_off, u32 ubwc_err_off);
+
+static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *cfg,
+ struct dpu_hw_sspp *ctx, u32 src_size_off,
+ u32 src_xy_off, u32 out_size_off, u32 out_xy_off)
+{
+ struct dpu_hw_blk_reg_map *c;
+ u32 src_size, src_xy, dst_size, dst_xy;
+
+ c = &ctx->hw;
+
+ /* src and dest rect programming */
+ src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
+ src_size = (drm_rect_height(&cfg->src_rect) << 16) |
+ drm_rect_width(&cfg->src_rect);
+ dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
+ dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
+ drm_rect_width(&cfg->dst_rect);
+
+ /* rectangle register programming */
+ DPU_REG_WRITE(c, src_size_off, src_size);
+ DPU_REG_WRITE(c, src_xy_off, src_xy);
+ DPU_REG_WRITE(c, out_size_off, dst_size);
+ DPU_REG_WRITE(c, out_xy_off, dst_xy);
+}
+
+void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
+ u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off);
+
+void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
+ bool danger_safe_en, u32 ctrl_off);
+
#endif /*_DPU_HW_SSPP_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 486be346d40d..3cf22ec62792 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -81,6 +81,13 @@ static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE;
#define QOS_CREQ_LUT_0 0x14
#define QOS_CREQ_LUT_1 0x18
+/* CMN_QOS_LUT */
+#define SSPP_CMN_QOS_CTRL 0x28
+#define SSPP_CMN_DANGER_LUT 0x2c
+#define SSPP_CMN_SAFE_LUT 0x30
+#define SSPP_CMN_CREQ_LUT_0 0x34
+#define SSPP_CMN_CREQ_LUT_1 0x38
+
/* QOS_QOS_CTRL */
#define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0)
#define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4)
@@ -475,6 +482,17 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
}
+void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
+ const struct dpu_hw_qos_cfg *cfg)
+{
+ DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut);
+ DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut);
+ DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut);
+ DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32);
+ DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL,
+ cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
+}
+
/*
* note: Aside from encoders, input_sel should be set to 0x0 by default
*/
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 67b08e99335d..1822ac699757 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -360,6 +360,9 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
bool qos_8lvl,
const struct dpu_hw_qos_cfg *cfg);
+void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
+ const struct dpu_hw_qos_cfg *cfg);
+
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
u32 misr_ctrl_offset, u8 input_sel);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 478a091aeccf..006dcc4a0dcc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -148,6 +148,15 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
cfg);
}
+static void dpu_hw_wb_setup_qos_lut_v13(struct dpu_hw_wb *ctx,
+ struct dpu_hw_qos_cfg *cfg)
+{
+ if (!ctx || !cfg)
+ return;
+
+ _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
+}
+
static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
const struct msm_format *fmt,
bool enable)
@@ -202,8 +211,12 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
if (test_bit(DPU_WB_XY_ROI_OFFSET, &features))
ops->setup_roi = dpu_hw_wb_roi;
- if (test_bit(DPU_WB_QOS, &features))
- ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
+ if (test_bit(DPU_WB_QOS, &features)) {
+ if (mdss_rev->core_major_ver >= 13)
+ ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut_v13;
+ else
+ ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
+ }
if (test_bit(DPU_WB_CDP, &features))
ops->setup_cdp = dpu_hw_wb_setup_cdp;
--
2.34.1On Mon, Dec 15, 2025 at 04:38:53PM +0800, yuanjie yang wrote:
> From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
>
> DPU version 13.0.0 introduces structural changes including
> register additions, removals, and relocations.
>
> Refactor SSPP-related code to be compatible with DPU 13.0.0
> modifications.
>
> Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> ---
We've fixed the order of the interrupts patch. Now you are adding SSPP
customization for 13.x _after_ adding the first 13.x support. Is that
supposed to work?
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 15 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 155 ++++++++++--------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 ++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
> 6 files changed, 191 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 0eb7cdf82ff9..f2aba9bdfcd3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -208,6 +208,18 @@ struct dpu_dsc_blk {
> u32 len;
> };
>
> +/**
> + * struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information
> + * @name: string name for debug purposes
> + * @base: offset of this sub-block relative to the block offset
> + * @len: register block length of this sub-block
> + */
> +struct dpu_sspp_v13_rec_blk {
> + char name[DPU_HW_BLK_NAME_LEN];
> + u32 base;
> + u32 len;
> +};
> +
> /**
> * enum dpu_qos_lut_usage - define QoS LUT use cases
> */
> @@ -294,7 +306,8 @@ struct dpu_sspp_sub_blks {
> u32 qseed_ver;
> struct dpu_scaler_blk scaler_blk;
> struct dpu_pp_blk csc_blk;
> -
> + struct dpu_sspp_v13_rec_blk sspp_rec0_blk;
> + struct dpu_sspp_v13_rec_blk sspp_rec1_blk;
Empty line afterwards.
> const u32 *format_list;
> u32 num_formats;
> const struct dpu_rotation_cfg *rotation_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 6f1fc790ad6d..7ed28009c463 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -145,11 +145,18 @@
> static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> - u32 mode_mask;
>
> if (!ctx)
> return;
>
> + dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE);
> +}
> +
> +void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
> + struct dpu_hw_sspp *ctx, u32 op_mode_off)
> +{
> + u32 mode_mask;
> +
> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
> /**
> * if rect index is RECT_SOLO, we cannot expect a
> @@ -158,7 +165,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
> */
> mode_mask = 0;
> } else {
> - mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE);
> + mode_mask = DPU_REG_READ(&ctx->hw, op_mode_off);
> mode_mask |= pipe->multirect_index;
> if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
> mode_mask |= BIT(2);
> @@ -166,11 +173,11 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
> mode_mask &= ~BIT(2);
> }
>
> - DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask);
> + DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask);
> }
>
> -static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
> - u32 mask, u8 en)
> +void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
> + u32 mask, u8 en)
> {
> const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
> u32 opmode;
> @@ -189,8 +196,8 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
> DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);
> }
>
> -static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
> - u32 mask, u8 en)
> +void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
> + u32 mask, u8 en)
> {
> const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
> u32 opmode;
> @@ -211,10 +218,6 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
> const struct msm_format *fmt, u32 flags)
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> - struct dpu_hw_blk_reg_map *c;
> - u32 chroma_samp, unpack, src_format;
> - u32 opmode = 0;
> - u32 fast_clear = 0;
> u32 op_mode_off, unpack_pat_off, format_off;
>
> if (!ctx || !fmt)
> @@ -231,7 +234,25 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
> format_off = SSPP_SRC_FORMAT_REC1;
> }
>
> + dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
> + unpack_pat_off, format_off,
> + SSPP_UBWC_STATIC_CTRL, SSPP_UBWC_ERROR_STATUS);
> +}
> +
> +void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
> + u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off,
> + u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off,
> + u32 ubwc_err_off)
> +{
> + struct dpu_hw_blk_reg_map *c;
> + u32 chroma_samp, unpack, src_format;
> + u32 opmode;
> + u32 fast_clear;
> + u8 core_major_ver;
> +
> c = &ctx->hw;
> + core_major_ver = ctx->mdss_ver->core_major_ver;
> +
> opmode = DPU_REG_READ(c, op_mode_off);
> opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
> MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
> @@ -273,31 +294,34 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
> if (MSM_FORMAT_IS_UBWC(fmt))
> opmode |= MDSS_MDP_OP_BWC_EN;
> src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
> - DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
> - DPU_FETCH_CONFIG_RESET_VALUE |
> - ctx->ubwc->highest_bank_bit << 18);
> +
> + if (core_major_ver < 13)
> + DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
> + DPU_FETCH_CONFIG_RESET_VALUE |
> + ctx->ubwc->highest_bank_bit << 18);
> +
This is not refactoring. Drop the conditions.
> switch (ctx->ubwc->ubwc_enc_version) {
> case UBWC_1_0:
> fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> - fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> - BIT(8) |
> - (ctx->ubwc->highest_bank_bit << 4));
> + DPU_REG_WRITE(c, ubwc_ctrl_off,
> + fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> + BIT(8) |
> + (ctx->ubwc->highest_bank_bit << 4));
I have asked to drop unrelated changes. You didn't. Why? You are
changing whitespaces for no reason. It's just a noise which hides the
actual change here.
> break;
> case UBWC_2_0:
> fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> - fast_clear | (ctx->ubwc->ubwc_swizzle) |
> - (ctx->ubwc->highest_bank_bit << 4));
> + DPU_REG_WRITE(c, ubwc_ctrl_off,
> + fast_clear | (ctx->ubwc->ubwc_swizzle) |
> + (ctx->ubwc->highest_bank_bit << 4));
> break;
> case UBWC_3_0:
> - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> - BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> - (ctx->ubwc->highest_bank_bit << 4));
> + DPU_REG_WRITE(c, ubwc_ctrl_off,
> + BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> + (ctx->ubwc->highest_bank_bit << 4));
> break;
> case UBWC_4_0:
> - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> - MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> + DPU_REG_WRITE(c, ubwc_ctrl_off,
> + MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> break;
> }
> }
> @@ -313,19 +337,18 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
>
> /* update scaler opmode, if appropriate */
> if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
> - _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
> - MSM_FORMAT_IS_YUV(fmt));
> + dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
> + MSM_FORMAT_IS_YUV(fmt));
> else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
> - _sspp_setup_csc10_opmode(ctx,
> - VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
> - MSM_FORMAT_IS_YUV(fmt));
> + dpu_hw_sspp_setup_csc10_opmode(ctx,
> + VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
> + MSM_FORMAT_IS_YUV(fmt));
Again, useless whitespace changes.
>
> DPU_REG_WRITE(c, format_off, src_format);
> DPU_REG_WRITE(c, unpack_pat_off, unpack);
> DPU_REG_WRITE(c, op_mode_off, opmode);
> -
Why?
> /* clear previous UBWC error */
> - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
> + DPU_REG_WRITE(c, ubwc_err_off, BIT(31));
> }
>
> static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> @@ -385,9 +408,9 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> tot_req_pixels[3]);
> }
>
> -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> - struct dpu_hw_scaler3_cfg *scaler3_cfg,
> - const struct msm_format *format)
> +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
> + const struct msm_format *format)
And here...
> {
> if (!ctx || !scaler3_cfg)
> return;
> @@ -405,15 +428,11 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> struct dpu_sw_pipe_cfg *cfg)
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> - struct dpu_hw_blk_reg_map *c;
> - u32 src_size, src_xy, dst_size, dst_xy;
> u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
>
> if (!ctx || !cfg)
> return;
>
> - c = &ctx->hw;
> -
> if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
> pipe->multirect_index == DPU_SSPP_RECT_0) {
> src_size_off = SSPP_SRC_SIZE;
> @@ -427,20 +446,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
> out_xy_off = SSPP_OUT_XY_REC1;
> }
>
> -
> - /* src and dest rect programming */
> - src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
> - src_size = (drm_rect_height(&cfg->src_rect) << 16) |
> - drm_rect_width(&cfg->src_rect);
> - dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
> - dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
> - drm_rect_width(&cfg->dst_rect);
> -
> - /* rectangle register programming */
> - DPU_REG_WRITE(c, src_size_off, src_size);
> - DPU_REG_WRITE(c, src_xy_off, src_xy);
> - DPU_REG_WRITE(c, out_size_off, dst_size);
> - DPU_REG_WRITE(c, out_xy_off, dst_xy);
> + dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
> + src_xy_off, out_size_off, out_xy_off);
> }
>
> static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> @@ -497,8 +504,8 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
> DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);
> }
>
> -static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
> - const struct dpu_csc_cfg *data)
> +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
> + const struct dpu_csc_cfg *data)
> {
> u32 offset;
> bool csc10 = false;
> @@ -519,21 +526,31 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
> static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
> {
> struct dpu_hw_sspp *ctx = pipe->sspp;
> - struct dpu_hw_fmt_layout cfg;
> + u32 const_clr_off;
>
> if (!ctx)
> return;
>
> + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
> + pipe->multirect_index == DPU_SSPP_RECT_0)
> + const_clr_off = SSPP_SRC_CONSTANT_COLOR;
> + else
> + const_clr_off = SSPP_SRC_CONSTANT_COLOR_REC1;
> +
> + dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
> +}
> +
> +void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
> + u32 color, struct dpu_hw_sspp *ctx,
> + u32 const_clr_off)
> +{
> + struct dpu_hw_fmt_layout cfg;
> +
> /* cleanup source addresses */
> memset(&cfg, 0, sizeof(cfg));
> ctx->ops.setup_sourceaddress(pipe, &cfg);
>
> - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
> - pipe->multirect_index == DPU_SSPP_RECT_0)
> - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color);
> - else
> - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1,
> - color);
> + DPU_REG_WRITE(&ctx->hw, const_clr_off, color);
> }
>
> static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
> @@ -547,14 +564,20 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
> cfg);
> }
>
> +void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
> + bool danger_safe_en, u32 ctrl_off)
> +{
> + DPU_REG_WRITE(&ctx->hw, ctrl_off,
> + danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
> +}
> +
> static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
> bool danger_safe_en)
> {
> if (!ctx)
> return;
>
> - DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
> - danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
> + dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL);
> }
>
> static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
> @@ -609,7 +632,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c,
> c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
>
> if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
> - c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
> + c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
>
> if (test_bit(DPU_SSPP_CDP, &features))
> c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index bdac5c04bf79..c6b19cb4d158 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -331,5 +331,57 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
> int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
> struct dentry *entry);
>
> +void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
> + u32 mask, u8 en);
> +
> +void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
> + u32 mask, u8 en);
> +
> +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> + struct dpu_hw_scaler3_cfg *scaler3_cfg,
> + const struct msm_format *format);
> +
> +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
> + const struct dpu_csc_cfg *data);
> +
> +void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
> + struct dpu_hw_sspp *ctx,
> + u32 op_mode_off);
> +
> +void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
> + u32 flags, struct dpu_hw_sspp *ctx,
> + u32 op_mode_off, u32 unpack_pat_off, u32 format_off,
> + u32 ubwc_ctrl_off, u32 ubwc_err_off);
> +
> +static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *cfg,
> + struct dpu_hw_sspp *ctx, u32 src_size_off,
> + u32 src_xy_off, u32 out_size_off, u32 out_xy_off)
> +{
> + struct dpu_hw_blk_reg_map *c;
> + u32 src_size, src_xy, dst_size, dst_xy;
> +
> + c = &ctx->hw;
> +
> + /* src and dest rect programming */
> + src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
> + src_size = (drm_rect_height(&cfg->src_rect) << 16) |
> + drm_rect_width(&cfg->src_rect);
> + dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
> + dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
> + drm_rect_width(&cfg->dst_rect);
> +
> + /* rectangle register programming */
> + DPU_REG_WRITE(c, src_size_off, src_size);
> + DPU_REG_WRITE(c, src_xy_off, src_xy);
> + DPU_REG_WRITE(c, out_size_off, dst_size);
> + DPU_REG_WRITE(c, out_xy_off, dst_xy);
> +}
> +
> +void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
> + u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off);
> +
> +void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
> + bool danger_safe_en, u32 ctrl_off);
> +
> #endif /*_DPU_HW_SSPP_H */
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> index 486be346d40d..3cf22ec62792 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> @@ -81,6 +81,13 @@ static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE;
> #define QOS_CREQ_LUT_0 0x14
> #define QOS_CREQ_LUT_1 0x18
>
> +/* CMN_QOS_LUT */
> +#define SSPP_CMN_QOS_CTRL 0x28
> +#define SSPP_CMN_DANGER_LUT 0x2c
> +#define SSPP_CMN_SAFE_LUT 0x30
> +#define SSPP_CMN_CREQ_LUT_0 0x34
> +#define SSPP_CMN_CREQ_LUT_1 0x38
> +
> /* QOS_QOS_CTRL */
> #define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0)
> #define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4)
> @@ -475,6 +482,17 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
> cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
> }
>
> +void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
> + const struct dpu_hw_qos_cfg *cfg)
It's definitely not a part of refactoring. Why is it a part of this
patch?
> +{
> + DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut);
> + DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut);
> + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut);
> + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32);
> + DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL,
> + cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
> +}
> +
> /*
> * note: Aside from encoders, input_sel should be set to 0x0 by default
> */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> index 67b08e99335d..1822ac699757 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> @@ -360,6 +360,9 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
> bool qos_8lvl,
> const struct dpu_hw_qos_cfg *cfg);
>
> +void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
> + const struct dpu_hw_qos_cfg *cfg);
> +
> void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
> u32 misr_ctrl_offset, u8 input_sel);
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> index 478a091aeccf..006dcc4a0dcc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> @@ -148,6 +148,15 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
> cfg);
> }
>
> +static void dpu_hw_wb_setup_qos_lut_v13(struct dpu_hw_wb *ctx,
> + struct dpu_hw_qos_cfg *cfg)
> +{
> + if (!ctx || !cfg)
> + return;
> +
> + _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
> +}
> +
> static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
> const struct msm_format *fmt,
> bool enable)
> @@ -202,8 +211,12 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
> if (test_bit(DPU_WB_XY_ROI_OFFSET, &features))
> ops->setup_roi = dpu_hw_wb_roi;
>
> - if (test_bit(DPU_WB_QOS, &features))
> - ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
> + if (test_bit(DPU_WB_QOS, &features)) {
> + if (mdss_rev->core_major_ver >= 13)
> + ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut_v13;
> + else
> + ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
> + }
>
> if (test_bit(DPU_WB_CDP, &features))
> ops->setup_cdp = dpu_hw_wb_setup_cdp;
> --
> 2.34.1
>
--
With best wishes
Dmitry
On Mon, Dec 15, 2025 at 10:08:22PM +0200, Dmitry Baryshkov wrote:
> On Mon, Dec 15, 2025 at 04:38:53PM +0800, yuanjie yang wrote:
> > From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> >
> > DPU version 13.0.0 introduces structural changes including
> > register additions, removals, and relocations.
> >
> > Refactor SSPP-related code to be compatible with DPU 13.0.0
> > modifications.
> >
> > Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > ---
>
> We've fixed the order of the interrupts patch. Now you are adding SSPP
> customization for 13.x _after_ adding the first 13.x support. Is that
> supposed to work?
Yes, will reorganize order.
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 15 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 155 ++++++++++--------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 ++++++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 ++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
> > 6 files changed, 191 insertions(+), 69 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > switch (ctx->ubwc->ubwc_enc_version) {
> > case UBWC_1_0:
> > fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > - fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> > - BIT(8) |
> > - (ctx->ubwc->highest_bank_bit << 4));
> > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > + fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> > + BIT(8) |
> > + (ctx->ubwc->highest_bank_bit << 4));
>
> I have asked to drop unrelated changes. You didn't. Why? You are
> changing whitespaces for no reason. It's just a noise which hides the
> actual change here.
here ubwc reg layout change in DPU 13.
ubwc_ctrl_off
veriosn < 13
reg: SSPP_UBWC_STATIC_CTRL
verison >= 13
reg: SSPP_REC_UBWC_STATIC_CTRL
So I do some fix.
> > break;
> > case UBWC_2_0:
> > fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > - fast_clear | (ctx->ubwc->ubwc_swizzle) |
> > - (ctx->ubwc->highest_bank_bit << 4));
> > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > + fast_clear | (ctx->ubwc->ubwc_swizzle) |
> > + (ctx->ubwc->highest_bank_bit << 4));
> > break;
> > case UBWC_3_0:
> > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > - BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> > - (ctx->ubwc->highest_bank_bit << 4));
> > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > + BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> > + (ctx->ubwc->highest_bank_bit << 4));
> > break;
> > case UBWC_4_0:
> > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > - MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > + MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> > break;
> > }
> > }
> > @@ -313,19 +337,18 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
> >
> > /* update scaler opmode, if appropriate */
> > if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
> > - _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
> > - MSM_FORMAT_IS_YUV(fmt));
> > + dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
> > + MSM_FORMAT_IS_YUV(fmt));
> > else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
> > - _sspp_setup_csc10_opmode(ctx,
> > - VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
> > - MSM_FORMAT_IS_YUV(fmt));
> > + dpu_hw_sspp_setup_csc10_opmode(ctx,
> > + VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
> > + MSM_FORMAT_IS_YUV(fmt));
>
> Again, useless whitespace changes.
checkpatch.pl says here is alignment issuse, so I do this fix.
> >
> > DPU_REG_WRITE(c, format_off, src_format);
> > DPU_REG_WRITE(c, unpack_pat_off, unpack);
> > DPU_REG_WRITE(c, op_mode_off, opmode);
> > -
>
> Why?
yes, will drop "-" diff.
> > /* clear previous UBWC error */
> > - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
> > + DPU_REG_WRITE(c, ubwc_err_off, BIT(31));
> > }
> >
> > static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> > @@ -385,9 +408,9 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> > tot_req_pixels[3]);
> > }
> >
> > -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> > - struct dpu_hw_scaler3_cfg *scaler3_cfg,
> > - const struct msm_format *format)
> > +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> > + struct dpu_hw_scaler3_cfg *scaler3_cfg,
> > + const struct msm_format *format)
>
> And here...
checkpatch.pl says here is alignment issuse, so I do this fix.
Thanks,
Yuanjie
> --
> With best wishes
> Dmitry
On Tue, Dec 16, 2025 at 02:56:31PM +0800, yuanjiey wrote:
> On Mon, Dec 15, 2025 at 10:08:22PM +0200, Dmitry Baryshkov wrote:
> > On Mon, Dec 15, 2025 at 04:38:53PM +0800, yuanjie yang wrote:
> > > From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > >
> > > DPU version 13.0.0 introduces structural changes including
> > > register additions, removals, and relocations.
> > >
> > > Refactor SSPP-related code to be compatible with DPU 13.0.0
> > > modifications.
> > >
> > > Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > > Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > > ---
> >
> > We've fixed the order of the interrupts patch. Now you are adding SSPP
> > customization for 13.x _after_ adding the first 13.x support. Is that
> > supposed to work?
>
> Yes, will reorganize order.
And after comparing with v2, I'm really surprised. It was better before
and then you changed the order of the patches. Why? You were asked to
split it, but not to move it to the end.
>
>
> > > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 15 +-
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 155 ++++++++++--------
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 ++++++
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 ++
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
> > > 6 files changed, 191 insertions(+), 69 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > > switch (ctx->ubwc->ubwc_enc_version) {
> > > case UBWC_1_0:
> > > fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > > - fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> > > - BIT(8) |
> > > - (ctx->ubwc->highest_bank_bit << 4));
> > > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > > + fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> > > + BIT(8) |
> > > + (ctx->ubwc->highest_bank_bit << 4));
> >
> > I have asked to drop unrelated changes. You didn't. Why? You are
> > changing whitespaces for no reason. It's just a noise which hides the
> > actual change here.
>
> here ubwc reg layout change in DPU 13.
>
> ubwc_ctrl_off
> veriosn < 13
> reg: SSPP_UBWC_STATIC_CTRL
> verison >= 13
> reg: SSPP_REC_UBWC_STATIC_CTRL
>
> So I do some fix.
What does it have to do with the whitespaces? Fix _one_ line.
>
> > > break;
> > > case UBWC_2_0:
> > > fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > > - fast_clear | (ctx->ubwc->ubwc_swizzle) |
> > > - (ctx->ubwc->highest_bank_bit << 4));
> > > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > > + fast_clear | (ctx->ubwc->ubwc_swizzle) |
> > > + (ctx->ubwc->highest_bank_bit << 4));
> > > break;
> > > case UBWC_3_0:
> > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > > - BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> > > - (ctx->ubwc->highest_bank_bit << 4));
> > > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > > + BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> > > + (ctx->ubwc->highest_bank_bit << 4));
> > > break;
> > > case UBWC_4_0:
> > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > > - MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> > > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > > + MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> > > break;
> > > }
> > > }
> > > @@ -313,19 +337,18 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
> > >
> > > /* update scaler opmode, if appropriate */
> > > if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
> > > - _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
> > > - MSM_FORMAT_IS_YUV(fmt));
> > > + dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
> > > + MSM_FORMAT_IS_YUV(fmt));
> > > else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
> > > - _sspp_setup_csc10_opmode(ctx,
> > > - VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
> > > - MSM_FORMAT_IS_YUV(fmt));
> > > + dpu_hw_sspp_setup_csc10_opmode(ctx,
> > > + VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
> > > + MSM_FORMAT_IS_YUV(fmt));
> >
> > Again, useless whitespace changes.
> checkpatch.pl says here is alignment issuse, so I do this fix.
The issue was present before your patch. If you want to fix it, fix it
in the separate patch or ignore it.
>
> > >
> > > DPU_REG_WRITE(c, format_off, src_format);
> > > DPU_REG_WRITE(c, unpack_pat_off, unpack);
> > > DPU_REG_WRITE(c, op_mode_off, opmode);
> > > -
> >
> > Why?
>
> yes, will drop "-" diff.
>
> > > /* clear previous UBWC error */
> > > - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
> > > + DPU_REG_WRITE(c, ubwc_err_off, BIT(31));
> > > }
> > >
> > > static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> > > @@ -385,9 +408,9 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> > > tot_req_pixels[3]);
> > > }
> > >
> > > -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> > > - struct dpu_hw_scaler3_cfg *scaler3_cfg,
> > > - const struct msm_format *format)
> > > +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> > > + struct dpu_hw_scaler3_cfg *scaler3_cfg,
> > > + const struct msm_format *format)
> >
> > And here...
> checkpatch.pl says here is alignment issuse, so I do this fix.
And I'm asking you to don't do it. Don't clutter the patch with
unrelated changes (and whitespace / alignment changes are generally
unrelated).
--
With best wishes
Dmitry
On Tue, Dec 16, 2025 at 04:22:32PM +0200, Dmitry Baryshkov wrote:
> On Tue, Dec 16, 2025 at 02:56:31PM +0800, yuanjiey wrote:
> > On Mon, Dec 15, 2025 at 10:08:22PM +0200, Dmitry Baryshkov wrote:
> > > On Mon, Dec 15, 2025 at 04:38:53PM +0800, yuanjie yang wrote:
> > > > From: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > > >
> > > > DPU version 13.0.0 introduces structural changes including
> > > > register additions, removals, and relocations.
> > > >
> > > > Refactor SSPP-related code to be compatible with DPU 13.0.0
> > > > modifications.
> > > >
> > > > Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > > > Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> > > > Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
> > > > ---
> > >
> > > We've fixed the order of the interrupts patch. Now you are adding SSPP
> > > customization for 13.x _after_ adding the first 13.x support. Is that
> > > supposed to work?
> >
> > Yes, will reorganize order.
>
> And after comparing with v2, I'm really surprised. It was better before
> and then you changed the order of the patches. Why? You were asked to
> split it, but not to move it to the end.
I make the mistake.
Sure, I will keep the v2 patch order in next patch.
> >
> >
> > > > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 15 +-
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 155 ++++++++++--------
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 ++++++
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 ++
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 +
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +-
> > > > 6 files changed, 191 insertions(+), 69 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > > > switch (ctx->ubwc->ubwc_enc_version) {
> > > > case UBWC_1_0:
> > > > fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> > > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > > > - fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> > > > - BIT(8) |
> > > > - (ctx->ubwc->highest_bank_bit << 4));
> > > > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > > > + fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
> > > > + BIT(8) |
> > > > + (ctx->ubwc->highest_bank_bit << 4));
> > >
> > > I have asked to drop unrelated changes. You didn't. Why? You are
> > > changing whitespaces for no reason. It's just a noise which hides the
> > > actual change here.
> >
> > here ubwc reg layout change in DPU 13.
> >
> > ubwc_ctrl_off
> > veriosn < 13
> > reg: SSPP_UBWC_STATIC_CTRL
> > verison >= 13
> > reg: SSPP_REC_UBWC_STATIC_CTRL
> >
> > So I do some fix.
>
> What does it have to do with the whitespaces? Fix _one_ line.
get it, will drop unrelated whitespaces.
> >
> > > > break;
> > > > case UBWC_2_0:
> > > > fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> > > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > > > - fast_clear | (ctx->ubwc->ubwc_swizzle) |
> > > > - (ctx->ubwc->highest_bank_bit << 4));
> > > > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > > > + fast_clear | (ctx->ubwc->ubwc_swizzle) |
> > > > + (ctx->ubwc->highest_bank_bit << 4));
> > > > break;
> > > > case UBWC_3_0:
> > > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > > > - BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> > > > - (ctx->ubwc->highest_bank_bit << 4));
> > > > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > > > + BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> > > > + (ctx->ubwc->highest_bank_bit << 4));
> > > > break;
> > > > case UBWC_4_0:
> > > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> > > > - MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> > > > + DPU_REG_WRITE(c, ubwc_ctrl_off,
> > > > + MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> > > > break;
> > > > }
> > > > }
> > > > @@ -313,19 +337,18 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
> > > >
> > > > /* update scaler opmode, if appropriate */
> > > > if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
> > > > - _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
> > > > - MSM_FORMAT_IS_YUV(fmt));
> > > > + dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
> > > > + MSM_FORMAT_IS_YUV(fmt));
> > > > else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
> > > > - _sspp_setup_csc10_opmode(ctx,
> > > > - VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
> > > > - MSM_FORMAT_IS_YUV(fmt));
> > > > + dpu_hw_sspp_setup_csc10_opmode(ctx,
> > > > + VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
> > > > + MSM_FORMAT_IS_YUV(fmt));
> > >
> > > Again, useless whitespace changes.
> > checkpatch.pl says here is alignment issuse, so I do this fix.
>
> The issue was present before your patch. If you want to fix it, fix it
> in the separate patch or ignore it.
get it, will drop unrelated whitespaces.
> >
> > > >
> > > > DPU_REG_WRITE(c, format_off, src_format);
> > > > DPU_REG_WRITE(c, unpack_pat_off, unpack);
> > > > DPU_REG_WRITE(c, op_mode_off, opmode);
> > > > -
> > >
> > > Why?
> >
> > yes, will drop "-" diff.
> >
> > > > /* clear previous UBWC error */
> > > > - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
> > > > + DPU_REG_WRITE(c, ubwc_err_off, BIT(31));
> > > > }
> > > >
> > > > static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> > > > @@ -385,9 +408,9 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
> > > > tot_req_pixels[3]);
> > > > }
> > > >
> > > > -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> > > > - struct dpu_hw_scaler3_cfg *scaler3_cfg,
> > > > - const struct msm_format *format)
> > > > +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
> > > > + struct dpu_hw_scaler3_cfg *scaler3_cfg,
> > > > + const struct msm_format *format)
> > >
> > > And here...
> > checkpatch.pl says here is alignment issuse, so I do this fix.
>
> And I'm asking you to don't do it. Don't clutter the patch with
> unrelated changes (and whitespace / alignment changes are generally
> unrelated).
>
> --
> With best wishes
> Dmitry
Thanks,
Yuanjie
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