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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f1bd6b50afsm90557971cf.21.2025.12.15.00.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Dec 2025 00:41:09 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, yongxing.mou@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com Subject: [PATCH v3 10/11] drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0 Date: Mon, 15 Dec 2025 16:38:53 +0800 Message-Id: <20251215083854.577-11-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215083854.577-1-yuanjie.yang@oss.qualcomm.com> References: <20251215083854.577-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE1MDA3MiBTYWx0ZWRfX5VygJC0nL00R xMEEsuf9UepLVNS9SQAmoDCbd9iZfJqWLTnm/J5I6xnkU+uBVpudeNcnijKl4BRR9Sm1L+//fgG hxfU31xUs2S24bVuSCu4J2INs+te0JAEXOphrjkysUWTwfie5RMOamUoZ7r7Co67jkubtO8Uoxz fzSVcCwsxPIljkN3UeTJKvU50eI4CRqvcWX3qCKsOFuQmMjQJ8sYq1ssNXz740XfeJMqX6hUNnZ +lVcyU1tENmUuVBmsf+q6y7MU86MRVc97JmIPK8GUmdQteRrAvHcCe81wQLxHJsg4ereQ0XqKoc xdW5pmLstABSKiDHGbxGwoHDr45YGeMFnJ3TAnSSjIbYa5Jg0Nlf19BGCp/iiPO7XqZ2Ncq4Hf0 ynjWwtdMo7cnpUi91ADclWcSm9pQ5A== X-Proofpoint-ORIG-GUID: ZpjO64p2pUknHgFw25cRKckWZoSm2JwJ X-Proofpoint-GUID: ZpjO64p2pUknHgFw25cRKckWZoSm2JwJ X-Authority-Analysis: v=2.4 cv=aOf9aL9m c=1 sm=1 tr=0 ts=693fc9a7 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ZMRFE71WIASCzucPcdAA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-15_01,2025-12-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512150072 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang DPU version 13.0.0 introduces structural changes including register additions, removals, and relocations. Refactor SSPP-related code to be compatible with DPU 13.0.0 modifications. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 15 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 155 ++++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 ++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +- 6 files changed, 191 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 0eb7cdf82ff9..f2aba9bdfcd3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -208,6 +208,18 @@ struct dpu_dsc_blk { u32 len; }; =20 +/** + * struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block + */ +struct dpu_sspp_v13_rec_blk { + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; +}; + /** * enum dpu_qos_lut_usage - define QoS LUT use cases */ @@ -294,7 +306,8 @@ struct dpu_sspp_sub_blks { u32 qseed_ver; struct dpu_scaler_blk scaler_blk; struct dpu_pp_blk csc_blk; - + struct dpu_sspp_v13_rec_blk sspp_rec0_blk; + struct dpu_sspp_v13_rec_blk sspp_rec1_blk; const u32 *format_list; u32 num_formats; const struct dpu_rotation_cfg *rotation_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 6f1fc790ad6d..7ed28009c463 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -145,11 +145,18 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - u32 mode_mask; =20 if (!ctx) return; =20 + dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE); +} + +void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp *ctx, u32 op_mode_off) +{ + u32 mode_mask; + if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO) { /** * if rect index is RECT_SOLO, we cannot expect a @@ -158,7 +165,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_p= ipe *pipe) */ mode_mask =3D 0; } else { - mode_mask =3D DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE); + mode_mask =3D DPU_REG_READ(&ctx->hw, op_mode_off); mode_mask |=3D pipe->multirect_index; if (pipe->multirect_mode =3D=3D DPU_SSPP_MULTIRECT_TIME_MX) mode_mask |=3D BIT(2); @@ -166,11 +173,11 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw= _pipe *pipe) mode_mask &=3D ~BIT(2); } =20 - DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask); + DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask); } =20 -static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, - u32 mask, u8 en) +void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en) { const struct dpu_sspp_sub_blks *sblk =3D ctx->cap->sblk; u32 opmode; @@ -189,8 +196,8 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode); } =20 -static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, - u32 mask, u8 en) +void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en) { const struct dpu_sspp_sub_blks *sblk =3D ctx->cap->sblk; u32 opmode; @@ -211,10 +218,6 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pip= e *pipe, const struct msm_format *fmt, u32 flags) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_blk_reg_map *c; - u32 chroma_samp, unpack, src_format; - u32 opmode =3D 0; - u32 fast_clear =3D 0; u32 op_mode_off, unpack_pat_off, format_off; =20 if (!ctx || !fmt) @@ -231,7 +234,25 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pip= e *pipe, format_off =3D SSPP_SRC_FORMAT_REC1; } =20 + dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off, + unpack_pat_off, format_off, + SSPP_UBWC_STATIC_CTRL, SSPP_UBWC_ERROR_STATUS); +} + +void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_f= ormat *fmt, + u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off, + u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off, + u32 ubwc_err_off) +{ + struct dpu_hw_blk_reg_map *c; + u32 chroma_samp, unpack, src_format; + u32 opmode; + u32 fast_clear; + u8 core_major_ver; + c =3D &ctx->hw; + core_major_ver =3D ctx->mdss_ver->core_major_ver; + opmode =3D DPU_REG_READ(c, op_mode_off); opmode &=3D ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); @@ -273,31 +294,34 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, if (MSM_FORMAT_IS_UBWC(fmt)) opmode |=3D MDSS_MDP_OP_BWC_EN; src_format |=3D (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ - DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, - DPU_FETCH_CONFIG_RESET_VALUE | - ctx->ubwc->highest_bank_bit << 18); + + if (core_major_ver < 13) + DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, + DPU_FETCH_CONFIG_RESET_VALUE | + ctx->ubwc->highest_bank_bit << 18); + switch (ctx->ubwc->ubwc_enc_version) { case UBWC_1_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | - BIT(8) | - (ctx->ubwc->highest_bank_bit << 4)); + DPU_REG_WRITE(c, ubwc_ctrl_off, + fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | + BIT(8) | + (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_2_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - fast_clear | (ctx->ubwc->ubwc_swizzle) | - (ctx->ubwc->highest_bank_bit << 4)); + DPU_REG_WRITE(c, ubwc_ctrl_off, + fast_clear | (ctx->ubwc->ubwc_swizzle) | + (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_3_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - BIT(30) | (ctx->ubwc->ubwc_swizzle) | - (ctx->ubwc->highest_bank_bit << 4)); + DPU_REG_WRITE(c, ubwc_ctrl_off, + BIT(30) | (ctx->ubwc->ubwc_swizzle) | + (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_4_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); + DPU_REG_WRITE(c, ubwc_ctrl_off, + MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); break; } } @@ -313,19 +337,18 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, =20 /* update scaler opmode, if appropriate */ if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) - _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, - MSM_FORMAT_IS_YUV(fmt)); + dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, + MSM_FORMAT_IS_YUV(fmt)); else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) - _sspp_setup_csc10_opmode(ctx, - VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, - MSM_FORMAT_IS_YUV(fmt)); + dpu_hw_sspp_setup_csc10_opmode(ctx, + VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, + MSM_FORMAT_IS_YUV(fmt)); =20 DPU_REG_WRITE(c, format_off, src_format); DPU_REG_WRITE(c, unpack_pat_off, unpack); DPU_REG_WRITE(c, op_mode_off, opmode); - /* clear previous UBWC error */ - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31)); + DPU_REG_WRITE(c, ubwc_err_off, BIT(31)); } =20 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, @@ -385,9 +408,9 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_s= spp *ctx, tot_req_pixels[3]); } =20 -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, - struct dpu_hw_scaler3_cfg *scaler3_cfg, - const struct msm_format *format) +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct msm_format *format) { if (!ctx || !scaler3_cfg) return; @@ -405,15 +428,11 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pip= e *pipe, struct dpu_sw_pipe_cfg *cfg) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_blk_reg_map *c; - u32 src_size, src_xy, dst_size, dst_xy; u32 src_size_off, src_xy_off, out_size_off, out_xy_off; =20 if (!ctx || !cfg) return; =20 - c =3D &ctx->hw; - if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) { src_size_off =3D SSPP_SRC_SIZE; @@ -427,20 +446,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe= *pipe, out_xy_off =3D SSPP_OUT_XY_REC1; } =20 - - /* src and dest rect programming */ - src_xy =3D (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; - src_size =3D (drm_rect_height(&cfg->src_rect) << 16) | - drm_rect_width(&cfg->src_rect); - dst_xy =3D (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; - dst_size =3D (drm_rect_height(&cfg->dst_rect) << 16) | - drm_rect_width(&cfg->dst_rect); - - /* rectangle register programming */ - DPU_REG_WRITE(c, src_size_off, src_size); - DPU_REG_WRITE(c, src_xy_off, src_xy); - DPU_REG_WRITE(c, out_size_off, dst_size); - DPU_REG_WRITE(c, out_xy_off, dst_xy); + dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off, + src_xy_off, out_size_off, out_xy_off); } =20 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, @@ -497,8 +504,8 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_= sw_pipe *pipe, DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1); } =20 -static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, - const struct dpu_csc_cfg *data) +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, + const struct dpu_csc_cfg *data) { u32 offset; bool csc10 =3D false; @@ -519,21 +526,31 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp = *ctx, static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 colo= r) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_fmt_layout cfg; + u32 const_clr_off; =20 if (!ctx) return; =20 + if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || + pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) + const_clr_off =3D SSPP_SRC_CONSTANT_COLOR; + else + const_clr_off =3D SSPP_SRC_CONSTANT_COLOR_REC1; + + dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off); +} + +void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe, + u32 color, struct dpu_hw_sspp *ctx, + u32 const_clr_off) +{ + struct dpu_hw_fmt_layout cfg; + /* cleanup source addresses */ memset(&cfg, 0, sizeof(cfg)); ctx->ops.setup_sourceaddress(pipe, &cfg); =20 - if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || - pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color); - else - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1, - color); + DPU_REG_WRITE(&ctx->hw, const_clr_off, color); } =20 static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx, @@ -547,14 +564,20 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_s= spp *ctx, cfg); } =20 +void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx, + bool danger_safe_en, u32 ctrl_off) +{ + DPU_REG_WRITE(&ctx->hw, ctrl_off, + danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0); +} + static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, bool danger_safe_en) { if (!ctx) return; =20 - DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL, - danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0); + dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL); } =20 static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, @@ -609,7 +632,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c, c->ops.setup_multirect =3D dpu_hw_sspp_setup_multirect; =20 if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features)) - c->ops.setup_scaler =3D _dpu_hw_sspp_setup_scaler3; + c->ops.setup_scaler =3D dpu_hw_sspp_setup_scaler3; =20 if (test_bit(DPU_SSPP_CDP, &features)) c->ops.setup_cdp =3D dpu_hw_sspp_setup_cdp; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index bdac5c04bf79..c6b19cb4d158 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -331,5 +331,57 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device= *dev, int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms = *kms, struct dentry *entry); =20 +void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en); + +void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en); + +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct msm_format *format); + +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, + const struct dpu_csc_cfg *data); + +void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp *ctx, + u32 op_mode_off); + +void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_f= ormat *fmt, + u32 flags, struct dpu_hw_sspp *ctx, + u32 op_mode_off, u32 unpack_pat_off, u32 format_off, + u32 ubwc_ctrl_off, u32 ubwc_err_off); + +static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struc= t dpu_sw_pipe_cfg *cfg, + struct dpu_hw_sspp *ctx, u32 src_size_off, + u32 src_xy_off, u32 out_size_off, u32 out_xy_off) +{ + struct dpu_hw_blk_reg_map *c; + u32 src_size, src_xy, dst_size, dst_xy; + + c =3D &ctx->hw; + + /* src and dest rect programming */ + src_xy =3D (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; + src_size =3D (drm_rect_height(&cfg->src_rect) << 16) | + drm_rect_width(&cfg->src_rect); + dst_xy =3D (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; + dst_size =3D (drm_rect_height(&cfg->dst_rect) << 16) | + drm_rect_width(&cfg->dst_rect); + + /* rectangle register programming */ + DPU_REG_WRITE(c, src_size_off, src_size); + DPU_REG_WRITE(c, src_xy_off, src_xy); + DPU_REG_WRITE(c, out_size_off, dst_size); + DPU_REG_WRITE(c, out_xy_off, dst_xy); +} + +void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe, + u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off); + +void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx, + bool danger_safe_en, u32 ctrl_off); + #endif /*_DPU_HW_SSPP_H */ =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.c index 486be346d40d..3cf22ec62792 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -81,6 +81,13 @@ static u32 dpu_hw_util_log_mask =3D DPU_DBG_MASK_NONE; #define QOS_CREQ_LUT_0 0x14 #define QOS_CREQ_LUT_1 0x18 =20 +/* CMN_QOS_LUT */ +#define SSPP_CMN_QOS_CTRL 0x28 +#define SSPP_CMN_DANGER_LUT 0x2c +#define SSPP_CMN_SAFE_LUT 0x30 +#define SSPP_CMN_CREQ_LUT_0 0x34 +#define SSPP_CMN_CREQ_LUT_1 0x38 + /* QOS_QOS_CTRL */ #define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0) #define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4) @@ -475,6 +482,17 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *= c, u32 offset, cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); } =20 +void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c, + const struct dpu_hw_qos_cfg *cfg) +{ + DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut); + DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut); + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut); + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32); + DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL, + cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); +} + /* * note: Aside from encoders, input_sel should be set to 0x0 by default */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.h index 67b08e99335d..1822ac699757 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -360,6 +360,9 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c= , u32 offset, bool qos_8lvl, const struct dpu_hw_qos_cfg *cfg); =20 +void _dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c, + const struct dpu_hw_qos_cfg *cfg); + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32 misr_ctrl_offset, u8 input_sel); =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_wb.c index 478a091aeccf..006dcc4a0dcc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -148,6 +148,15 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *= ctx, cfg); } =20 +static void dpu_hw_wb_setup_qos_lut_v13(struct dpu_hw_wb *ctx, + struct dpu_hw_qos_cfg *cfg) +{ + if (!ctx || !cfg) + return; + + _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg); +} + static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx, const struct msm_format *fmt, bool enable) @@ -202,8 +211,12 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops, if (test_bit(DPU_WB_XY_ROI_OFFSET, &features)) ops->setup_roi =3D dpu_hw_wb_roi; =20 - if (test_bit(DPU_WB_QOS, &features)) - ops->setup_qos_lut =3D dpu_hw_wb_setup_qos_lut; + if (test_bit(DPU_WB_QOS, &features)) { + if (mdss_rev->core_major_ver >=3D 13) + ops->setup_qos_lut =3D dpu_hw_wb_setup_qos_lut_v13; + else + ops->setup_qos_lut =3D dpu_hw_wb_setup_qos_lut; + } =20 if (test_bit(DPU_WB_CDP, &features)) ops->setup_cdp =3D dpu_hw_wb_setup_cdp; --=20 2.34.1