The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three
DMAC instances. Compared to the previously supported RZ/V2H, these SoCs
are missing the error interrupt line and the reset lines, and they use
a different ICU IP.
This series depends on the ICU series [1].
[1]: https://lore.kernel.org/lkml/20251201112933.488801-1-cosmin-gabriel.tanislav.xa@renesas.com/
Cosmin Tanislav (6):
dmaengine: sh: rz_dmac: make error interrupt optional
dmaengine: sh: rz_dmac: make register_dma_req() chip-specific
dt-bindings: dma: renesas,rz-dmac: document RZ/{T2H,N2H}
dmaengine: sh: rz_dmac: add RZ/{T2H,N2H} support
arm64: dts: renesas: r9a09g077: add DMAC support
arm64: dts: renesas: r9a09g087: add DMAC support
.../bindings/dma/renesas,rz-dmac.yaml | 100 ++++++++++++++----
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 90 ++++++++++++++++
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 90 ++++++++++++++++
drivers/dma/sh/rz-dmac.c | 94 +++++++++-------
4 files changed, 317 insertions(+), 57 deletions(-)
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2.52.0