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[PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider

Luo Jie posted 5 patches 2 months, 1 week ago
There is a newer version of this series
[PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider
Posted by Luo Jie 2 months, 1 week ago 
The clk_cmn_pll_recalc_rate() function must account for the reference clock
divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
with a reference divider other than 1 calculate incorrect CMN PLL rates.
For example, on IPQ5332 where the reference divider is 2, the computed rate
becomes twice the actual output.

Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
applying the 2 * FACTOR scaling. This yields the correct rate calculation:
rate = (parent_rate / ref_div) * 2 * factor.

Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
IPQ5424, IPQ5018) that use ref_div = 1.

Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC")
Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
---
 drivers/clk/qcom/ipq-cmn-pll.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c
index dafbf5732048..c6180116e1fc 100644
--- a/drivers/clk/qcom/ipq-cmn-pll.c
+++ b/drivers/clk/qcom/ipq-cmn-pll.c
@@ -185,7 +185,7 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw,
 					     unsigned long parent_rate)
 {
 	struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw);
-	u32 val, factor;
+	u32 val, factor, ref_div;
 
 	/*
 	 * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted
@@ -193,8 +193,15 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw,
 	 */
 	regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val);
 	factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val);
+	if (unlikely(factor == 0))
+		factor = 1;
 
-	return parent_rate * 2 * factor;
+	regmap_read(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, &val);
+	ref_div = FIELD_GET(CMN_PLL_REFCLK_DIV, val);
+	if (unlikely(ref_div == 0))
+		ref_div = 1;
+
+	return div_u64((u64)parent_rate * 2 * factor, ref_div);
 }
 
 static int clk_cmn_pll_determine_rate(struct clk_hw *hw,

-- 
2.43.0
Re: [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider
Posted by Konrad Dybcio 2 months, 1 week ago 
On 11/28/25 9:40 AM, Luo Jie wrote:
> The clk_cmn_pll_recalc_rate() function must account for the reference clock
> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
> with a reference divider other than 1 calculate incorrect CMN PLL rates.
> For example, on IPQ5332 where the reference divider is 2, the computed rate
> becomes twice the actual output.
> 
> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
> applying the 2 * FACTOR scaling. This yields the correct rate calculation:
> rate = (parent_rate / ref_div) * 2 * factor.
> 
> Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
> IPQ5424, IPQ5018) that use ref_div = 1.

I'm not sure how to interpret this. Is the value fixed on these platforms
you mentioned, and always shows up as 0?

Konrad
Re: [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider
Posted by Jie Luo 2 months, 1 week ago 

On 11/28/2025 7:38 PM, Konrad Dybcio wrote:
> On 11/28/25 9:40 AM, Luo Jie wrote:
>> The clk_cmn_pll_recalc_rate() function must account for the reference clock
>> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
>> with a reference divider other than 1 calculate incorrect CMN PLL rates.
>> For example, on IPQ5332 where the reference divider is 2, the computed rate
>> becomes twice the actual output.
>>
>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
>> applying the 2 * FACTOR scaling. This yields the correct rate calculation:
>> rate = (parent_rate / ref_div) * 2 * factor.
>>
>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
>> IPQ5424, IPQ5018) that use ref_div = 1.
> 
> I'm not sure how to interpret this. Is the value fixed on these platforms
> you mentioned, and always shows up as 0?
> 
> Konrad

On these platforms the hardware ref_div register comes up with a value
of 1 by default. It is, however, still a programmable field and not
strictly fixed to 1.

The ref_div == 0 check in this patch is only meant as a safety net to
avoid a divide‑by‑zero in the rate calculation.
Re: [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider
Posted by Konrad Dybcio 2 months, 1 week ago 
On 11/28/25 3:29 PM, Jie Luo wrote:
> 
> 
> On 11/28/2025 7:38 PM, Konrad Dybcio wrote:
>> On 11/28/25 9:40 AM, Luo Jie wrote:
>>> The clk_cmn_pll_recalc_rate() function must account for the reference clock
>>> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
>>> with a reference divider other than 1 calculate incorrect CMN PLL rates.
>>> For example, on IPQ5332 where the reference divider is 2, the computed rate
>>> becomes twice the actual output.
>>>
>>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
>>> applying the 2 * FACTOR scaling. This yields the correct rate calculation:
>>> rate = (parent_rate / ref_div) * 2 * factor.
>>>
>>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
>>> IPQ5424, IPQ5018) that use ref_div = 1.
>>
>> I'm not sure how to interpret this. Is the value fixed on these platforms
>> you mentioned, and always shows up as 0?
>>
>> Konrad
> 
> On these platforms the hardware ref_div register comes up with a value
> of 1 by default. It is, however, still a programmable field and not
> strictly fixed to 1.
> 
> The ref_div == 0 check in this patch is only meant as a safety net to
> avoid a divide‑by‑zero in the rate calculation.

I think some sort of a warning/bugsplat would be good to have here,
however I see that clk-rcg2.c : clk_gfx3d_determine_rate() apparently
also silently fixes up a div0..

Konrad
Re: [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider
Posted by Jie Luo 2 months, 1 week ago 

On 12/1/2025 9:42 PM, Konrad Dybcio wrote:
> On 11/28/25 3:29 PM, Jie Luo wrote:
>>
>>
>> On 11/28/2025 7:38 PM, Konrad Dybcio wrote:
>>> On 11/28/25 9:40 AM, Luo Jie wrote:
>>>> The clk_cmn_pll_recalc_rate() function must account for the reference clock
>>>> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
>>>> with a reference divider other than 1 calculate incorrect CMN PLL rates.
>>>> For example, on IPQ5332 where the reference divider is 2, the computed rate
>>>> becomes twice the actual output.
>>>>
>>>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
>>>> applying the 2 * FACTOR scaling. This yields the correct rate calculation:
>>>> rate = (parent_rate / ref_div) * 2 * factor.
>>>>
>>>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
>>>> IPQ5424, IPQ5018) that use ref_div = 1.
>>>
>>> I'm not sure how to interpret this. Is the value fixed on these platforms
>>> you mentioned, and always shows up as 0?
>>>
>>> Konrad
>>
>> On these platforms the hardware ref_div register comes up with a value
>> of 1 by default. It is, however, still a programmable field and not
>> strictly fixed to 1.
>>
>> The ref_div == 0 check in this patch is only meant as a safety net to
>> avoid a divide‑by‑zero in the rate calculation.
> 
> I think some sort of a warning/bugsplat would be good to have here,
> however I see that clk-rcg2.c : clk_gfx3d_determine_rate() apparently
> also silently fixes up a div0..
> 
> Konrad

I agree it would be better to at least flag this as an invalid
configuration. I can update the code to emit a warning (e.g. WARN_ON
(!ref_div) while still clamping ref_div to a sane value to avoid
crashing in production. That way we preserve the safety net but also
get some visibility if this ever happens.
Re: [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider
Posted by Konrad Dybcio 2 months, 1 week ago 
On 12/4/25 8:44 AM, Jie Luo wrote:
> 
> 
> On 12/1/2025 9:42 PM, Konrad Dybcio wrote:
>> On 11/28/25 3:29 PM, Jie Luo wrote:
>>>
>>>
>>> On 11/28/2025 7:38 PM, Konrad Dybcio wrote:
>>>> On 11/28/25 9:40 AM, Luo Jie wrote:
>>>>> The clk_cmn_pll_recalc_rate() function must account for the reference clock
>>>>> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
>>>>> with a reference divider other than 1 calculate incorrect CMN PLL rates.
>>>>> For example, on IPQ5332 where the reference divider is 2, the computed rate
>>>>> becomes twice the actual output.
>>>>>
>>>>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
>>>>> applying the 2 * FACTOR scaling. This yields the correct rate calculation:
>>>>> rate = (parent_rate / ref_div) * 2 * factor.
>>>>>
>>>>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
>>>>> IPQ5424, IPQ5018) that use ref_div = 1.
>>>>
>>>> I'm not sure how to interpret this. Is the value fixed on these platforms
>>>> you mentioned, and always shows up as 0?
>>>>
>>>> Konrad
>>>
>>> On these platforms the hardware ref_div register comes up with a value
>>> of 1 by default. It is, however, still a programmable field and not
>>> strictly fixed to 1.
>>>
>>> The ref_div == 0 check in this patch is only meant as a safety net to
>>> avoid a divide‑by‑zero in the rate calculation.
>>
>> I think some sort of a warning/bugsplat would be good to have here,
>> however I see that clk-rcg2.c : clk_gfx3d_determine_rate() apparently
>> also silently fixes up a div0..
>>
>> Konrad
> 
> I agree it would be better to at least flag this as an invalid
> configuration. I can update the code to emit a warning (e.g. WARN_ON
> (!ref_div) while still clamping ref_div to a sane value to avoid
> crashing in production. That way we preserve the safety net but also
> get some visibility if this ever happens.

if (WARN_ON(div == 0))

sounds good!

Konrad

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