Add support for firmware-managed resource states in the
Qualcomm DWC3 USB controller driver. On platforms
like sa8255p, where controller resources are abstracted
and managed collectively by firmware, the driver communicates
power management transitions using dedicated resource state
levels via dev_pm_opp_set_level().
Macros are introduced to represent key lifecycle events:
initialization, system and runtime suspend/resume, and exit.
The driver sets the appropriate resource state during probe,
remove, suspend, and resume operations, enabling bulk ON/OFF
transitions of grouped resources according to the
controller's operational state.
Signed-off-by: Sriram Dash <sriram.dash@oss.qualcomm.com>
Co-developed-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
Signed-off-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
---
drivers/usb/dwc3/dwc3-qcom.c | 97 ++++++++++++++++++++++++++++++++++++++++----
1 file changed, 88 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 9ac75547820d..9615ca6cfcae 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -13,6 +13,8 @@
#include <linux/kernel.h>
#include <linux/interconnect.h>
#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_opp.h>
#include <linux/phy/phy.h>
#include <linux/usb/of.h>
#include <linux/reset.h>
@@ -85,10 +87,48 @@ struct dwc3_qcom {
struct icc_path *icc_path_apps;
enum usb_role current_role;
+ bool fw_managed;
};
#define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc)
+/*
+ * QCOM DWC3 USB Controller: Firmware-Managed Resource State Levels
+ *
+ * On select Qualcomm platforms, the USB controller’s power-related
+ * resources including GDSC, reset lines, clocks, and interconnects
+ * are managed collectively by system firmware via SCMI. The driver
+ * signals the controller’s operational state to firmware using these
+ * levels, each mapped to a specific power management transition or
+ * lifecycle event:
+ *
+ * DWC3_QCOM_FW_MANAGED_INIT
+ * Enable GDSC, Assert and Deassert Resets, and turn ON all clocks
+ * and interconnects.
+ *
+ * DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME
+ * Enable GDSC and turn ON all clocks and interconnects.
+ *
+ * DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME
+ * Turn ON all clocks and interconnects.
+ *
+ * DWC3_QCOM_FW_MANAGED_EXIT
+ * Turn OFF all clocks and interconnects, Assert reset and disable GDSC.
+ *
+ * DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND
+ * Turn OFF all clocks and interconnects and disable GDSC.
+ *
+ * DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND
+ * Turn OFF clocks and interconnects.
+ */
+
+#define DWC3_QCOM_FW_MANAGED_INIT 1
+#define DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME 2
+#define DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME 3
+#define DWC3_QCOM_FW_MANAGED_EXIT 8
+#define DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND 9
+#define DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND 10
+
static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
{
u32 reg;
@@ -335,7 +375,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
dwc3_qcom_enable_port_interrupts(&qcom->ports[i]);
}
-static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
+static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup, pm_message_t msg)
{
u32 val;
int i, ret;
@@ -348,6 +388,13 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
}
+ if (qcom->fw_managed) {
+ if (PMSG_IS_AUTO(msg))
+ dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND);
+ else
+ dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND);
+ }
+
clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
ret = dwc3_qcom_interconnect_disable(qcom);
@@ -369,7 +416,7 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
return 0;
}
-static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
+static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup, pm_message_t msg)
{
int ret;
int i;
@@ -380,6 +427,18 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
if (dwc3_qcom_is_host(qcom) && wakeup)
dwc3_qcom_disable_interrupts(qcom);
+ if (qcom->fw_managed) {
+ if (PMSG_IS_AUTO(msg))
+ ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME);
+ else
+ ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME);
+
+ if (ret < 0) {
+ dev_err(qcom->dev, "Failed to Resume fw managed device\n");
+ return ret;
+ }
+ }
+
ret = clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks);
if (ret < 0)
return ret;
@@ -624,10 +683,18 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
qcom->dev = &pdev->dev;
+ qcom->fw_managed = device_get_match_data(dev);
+ if (qcom->fw_managed) {
+ ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_INIT);
+ if (ret < 0)
+ return ret;
+ }
+
qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
if (IS_ERR(qcom->resets)) {
- return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
- "failed to get resets\n");
+ dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
+ "failed to get resets\n");
+ goto resources_off;
}
ret = devm_clk_bulk_get_all(&pdev->dev, &qcom->clks);
@@ -638,7 +705,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
ret = reset_control_assert(qcom->resets);
if (ret) {
dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
- return ret;
+ goto resources_off;
}
usleep_range(10, 1000);
@@ -727,6 +794,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
clk_disable:
clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
+resources_off:
+ if (qcom->fw_managed)
+ dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT);
+
return ret;
}
@@ -739,6 +810,10 @@ static void dwc3_qcom_remove(struct platform_device *pdev)
return;
dwc3_core_remove(&qcom->dwc);
+
+ if (qcom->fw_managed)
+ dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT);
+
clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
dwc3_qcom_interconnect_exit(qcom);
@@ -756,7 +831,7 @@ static int dwc3_qcom_pm_suspend(struct device *dev)
if (ret)
return ret;
- ret = dwc3_qcom_suspend(qcom, wakeup);
+ ret = dwc3_qcom_suspend(qcom, wakeup, PMSG_SUSPEND);
if (ret)
return ret;
@@ -772,7 +847,7 @@ static int dwc3_qcom_pm_resume(struct device *dev)
bool wakeup = device_may_wakeup(dev);
int ret;
- ret = dwc3_qcom_resume(qcom, wakeup);
+ ret = dwc3_qcom_resume(qcom, wakeup, PMSG_RESUME);
if (ret)
return ret;
@@ -809,7 +884,7 @@ static int dwc3_qcom_runtime_suspend(struct device *dev)
if (ret)
return ret;
- return dwc3_qcom_suspend(qcom, true);
+ return dwc3_qcom_suspend(qcom, true, PMSG_AUTO_SUSPEND);
}
static int dwc3_qcom_runtime_resume(struct device *dev)
@@ -818,7 +893,7 @@ static int dwc3_qcom_runtime_resume(struct device *dev)
struct dwc3_qcom *qcom = to_dwc3_qcom(dwc);
int ret;
- ret = dwc3_qcom_resume(qcom, true);
+ ret = dwc3_qcom_resume(qcom, true, PMSG_AUTO_RESUME);
if (ret)
return ret;
@@ -839,6 +914,10 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
};
static const struct of_device_id dwc3_qcom_of_match[] = {
+ {
+ .compatible = "qcom,snps-dwc3-fw-managed",
+ .data = (void *)true,
+ },
{ .compatible = "qcom,snps-dwc3" },
{ }
};
--
2.34.1
Hi Sriram,
kernel test robot noticed the following build warnings:
url: https://github.com/intel-lab-lkp/linux/commits/Sriram-Dash/dt-bindings-usb-qcom-snps-dwc3-Add-support-for-firmware-managed-resources/20251127-183548
base: c77a6544d8a2364e4bee1b52890f577be27b7296
patch link: https://lore.kernel.org/r/20251127-controller_scmi_upstream-v1-2-38bcca513c28%40oss.qualcomm.com
patch subject: [PATCH 2/2] usb: dwc3: qcom: Support firmware-managed resource states for power management
config: nios2-randconfig-r071-20251204 (https://download.01.org/0day-ci/archive/20251206/202512060556.pgIgFNxx-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 8.5.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202512060556.pgIgFNxx-lkp@intel.com/
smatch warnings:
drivers/usb/dwc3/dwc3-qcom.c:801 dwc3_qcom_probe() error: uninitialized symbol 'ret'.
vim +/ret +801 drivers/usb/dwc3/dwc3-qcom.c
21188e8d6d7590 Krishna Kurapati 2025-09-07 668
2bc02355f8ba2c Lee Jones 2019-06-17 669 static int dwc3_qcom_probe(struct platform_device *pdev)
2bc02355f8ba2c Lee Jones 2019-06-17 670 {
1881a32fe14df8 Bjorn Andersson 2025-04-14 671 struct dwc3_probe_data probe_data = {};
2bc02355f8ba2c Lee Jones 2019-06-17 672 struct device *dev = &pdev->dev;
a4333c3a6ba9ca Manu Gautam 2018-05-09 673 struct dwc3_qcom *qcom;
1881a32fe14df8 Bjorn Andersson 2025-04-14 674 struct resource res;
1881a32fe14df8 Bjorn Andersson 2025-04-14 675 struct resource *r;
e33ebb133a245a Bjorn Andersson 2025-05-08 676 int ret;
a4333c3a6ba9ca Manu Gautam 2018-05-09 677 bool ignore_pipe_clk;
e3fafbd8e36530 Johan Hovold 2022-08-04 678 bool wakeup_source;
a4333c3a6ba9ca Manu Gautam 2018-05-09 679
a4333c3a6ba9ca Manu Gautam 2018-05-09 680 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
a4333c3a6ba9ca Manu Gautam 2018-05-09 681 if (!qcom)
a4333c3a6ba9ca Manu Gautam 2018-05-09 682 return -ENOMEM;
a4333c3a6ba9ca Manu Gautam 2018-05-09 683
a4333c3a6ba9ca Manu Gautam 2018-05-09 684 qcom->dev = &pdev->dev;
a4333c3a6ba9ca Manu Gautam 2018-05-09 685
79456073227880 Sriram Dash 2025-11-27 686 qcom->fw_managed = device_get_match_data(dev);
79456073227880 Sriram Dash 2025-11-27 687 if (qcom->fw_managed) {
79456073227880 Sriram Dash 2025-11-27 688 ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_INIT);
79456073227880 Sriram Dash 2025-11-27 689 if (ret < 0)
79456073227880 Sriram Dash 2025-11-27 690 return ret;
79456073227880 Sriram Dash 2025-11-27 691 }
79456073227880 Sriram Dash 2025-11-27 692
a4333c3a6ba9ca Manu Gautam 2018-05-09 693 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
a4333c3a6ba9ca Manu Gautam 2018-05-09 694 if (IS_ERR(qcom->resets)) {
79456073227880 Sriram Dash 2025-11-27 695 dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
60d5b71933c4f1 Andrew Halaney 2023-06-05 696 "failed to get resets\n");
ret = dev_err_probe()
79456073227880 Sriram Dash 2025-11-27 697 goto resources_off;
a4333c3a6ba9ca Manu Gautam 2018-05-09 698 }
a4333c3a6ba9ca Manu Gautam 2018-05-09 699
e33ebb133a245a Bjorn Andersson 2025-05-08 700 ret = devm_clk_bulk_get_all(&pdev->dev, &qcom->clks);
e33ebb133a245a Bjorn Andersson 2025-05-08 701 if (ret < 0)
e33ebb133a245a Bjorn Andersson 2025-05-08 702 return dev_err_probe(dev, ret, "failed to get clocks\n");
e33ebb133a245a Bjorn Andersson 2025-05-08 703 qcom->num_clocks = ret;
e33ebb133a245a Bjorn Andersson 2025-05-08 704
a4333c3a6ba9ca Manu Gautam 2018-05-09 705 ret = reset_control_assert(qcom->resets);
a4333c3a6ba9ca Manu Gautam 2018-05-09 706 if (ret) {
a4333c3a6ba9ca Manu Gautam 2018-05-09 707 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
79456073227880 Sriram Dash 2025-11-27 708 goto resources_off;
a4333c3a6ba9ca Manu Gautam 2018-05-09 709 }
a4333c3a6ba9ca Manu Gautam 2018-05-09 710
a4333c3a6ba9ca Manu Gautam 2018-05-09 711 usleep_range(10, 1000);
a4333c3a6ba9ca Manu Gautam 2018-05-09 712
a4333c3a6ba9ca Manu Gautam 2018-05-09 713 ret = reset_control_deassert(qcom->resets);
a4333c3a6ba9ca Manu Gautam 2018-05-09 714 if (ret) {
a4333c3a6ba9ca Manu Gautam 2018-05-09 715 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
ef8abc0ba49ce7 Krishna Kurapati 2025-07-09 716 return ret;
a4333c3a6ba9ca Manu Gautam 2018-05-09 717 }
a4333c3a6ba9ca Manu Gautam 2018-05-09 718
e33ebb133a245a Bjorn Andersson 2025-05-08 719 ret = clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks);
e33ebb133a245a Bjorn Andersson 2025-05-08 720 if (ret < 0)
ef8abc0ba49ce7 Krishna Kurapati 2025-07-09 721 return ret;
a4333c3a6ba9ca Manu Gautam 2018-05-09 722
1881a32fe14df8 Bjorn Andersson 2025-04-14 723 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4c0fca65d10548 Dan Carpenter 2025-04-23 724 if (!r) {
4c0fca65d10548 Dan Carpenter 2025-04-23 725 ret = -EINVAL;
1881a32fe14df8 Bjorn Andersson 2025-04-14 726 goto clk_disable;
4c0fca65d10548 Dan Carpenter 2025-04-23 727 }
1881a32fe14df8 Bjorn Andersson 2025-04-14 728 res = *r;
1881a32fe14df8 Bjorn Andersson 2025-04-14 729 res.end = res.start + SDM845_QSCRATCH_BASE_OFFSET;
1881a32fe14df8 Bjorn Andersson 2025-04-14 730
1881a32fe14df8 Bjorn Andersson 2025-04-14 731 qcom->qscratch_base = devm_ioremap(dev, res.end, SDM845_QSCRATCH_SIZE);
4c0fca65d10548 Dan Carpenter 2025-04-23 732 if (!qcom->qscratch_base) {
4c0fca65d10548 Dan Carpenter 2025-04-23 733 dev_err(dev, "failed to map qscratch region\n");
4c0fca65d10548 Dan Carpenter 2025-04-23 734 ret = -ENOMEM;
41717b88abf1ca Krishna Kurapati 2024-03-05 735 goto clk_disable;
a4333c3a6ba9ca Manu Gautam 2018-05-09 736 }
a4333c3a6ba9ca Manu Gautam 2018-05-09 737
2dc9f137e19426 Bjorn Andersson 2025-04-14 738 ret = dwc3_qcom_setup_irq(qcom, pdev);
2bc02355f8ba2c Lee Jones 2019-06-17 739 if (ret) {
2bc02355f8ba2c Lee Jones 2019-06-17 740 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
41717b88abf1ca Krishna Kurapati 2024-03-05 741 goto clk_disable;
a4333c3a6ba9ca Manu Gautam 2018-05-09 742 }
a4333c3a6ba9ca Manu Gautam 2018-05-09 743
a4333c3a6ba9ca Manu Gautam 2018-05-09 744 /*
a4333c3a6ba9ca Manu Gautam 2018-05-09 745 * Disable pipe_clk requirement if specified. Used when dwc3
a4333c3a6ba9ca Manu Gautam 2018-05-09 746 * operates without SSPHY and only HS/FS/LS modes are supported.
a4333c3a6ba9ca Manu Gautam 2018-05-09 747 */
a4333c3a6ba9ca Manu Gautam 2018-05-09 748 ignore_pipe_clk = device_property_read_bool(dev,
a4333c3a6ba9ca Manu Gautam 2018-05-09 749 "qcom,select-utmi-as-pipe-clk");
a4333c3a6ba9ca Manu Gautam 2018-05-09 750 if (ignore_pipe_clk)
a4333c3a6ba9ca Manu Gautam 2018-05-09 751 dwc3_qcom_select_utmi_clk(qcom);
a4333c3a6ba9ca Manu Gautam 2018-05-09 752
21188e8d6d7590 Krishna Kurapati 2025-09-07 753 qcom->mode = usb_get_dr_mode(dev);
21188e8d6d7590 Krishna Kurapati 2025-09-07 754
21188e8d6d7590 Krishna Kurapati 2025-09-07 755 if (qcom->mode == USB_DR_MODE_HOST) {
21188e8d6d7590 Krishna Kurapati 2025-09-07 756 qcom->current_role = USB_ROLE_HOST;
21188e8d6d7590 Krishna Kurapati 2025-09-07 757 } else if (qcom->mode == USB_DR_MODE_PERIPHERAL) {
21188e8d6d7590 Krishna Kurapati 2025-09-07 758 qcom->current_role = USB_ROLE_DEVICE;
21188e8d6d7590 Krishna Kurapati 2025-09-07 759 dwc3_qcom_vbus_override_enable(qcom, true);
21188e8d6d7590 Krishna Kurapati 2025-09-07 760 } else {
21188e8d6d7590 Krishna Kurapati 2025-09-07 761 if ((device_property_read_bool(dev, "usb-role-switch")) &&
21188e8d6d7590 Krishna Kurapati 2025-09-07 762 (usb_get_role_switch_default_mode(dev) == USB_DR_MODE_HOST))
21188e8d6d7590 Krishna Kurapati 2025-09-07 763 qcom->current_role = USB_ROLE_HOST;
21188e8d6d7590 Krishna Kurapati 2025-09-07 764 else
21188e8d6d7590 Krishna Kurapati 2025-09-07 765 qcom->current_role = USB_ROLE_DEVICE;
21188e8d6d7590 Krishna Kurapati 2025-09-07 766 }
21188e8d6d7590 Krishna Kurapati 2025-09-07 767
21188e8d6d7590 Krishna Kurapati 2025-09-07 768 qcom->dwc.glue_ops = &dwc3_qcom_glue_ops;
21188e8d6d7590 Krishna Kurapati 2025-09-07 769
1881a32fe14df8 Bjorn Andersson 2025-04-14 770 qcom->dwc.dev = dev;
1881a32fe14df8 Bjorn Andersson 2025-04-14 771 probe_data.dwc = &qcom->dwc;
1881a32fe14df8 Bjorn Andersson 2025-04-14 772 probe_data.res = &res;
1881a32fe14df8 Bjorn Andersson 2025-04-14 773 probe_data.ignore_clocks_and_resets = true;
7298c06d58e23c Frank Li 2025-09-29 774 probe_data.properties = DWC3_DEFAULT_PROPERTIES;
1881a32fe14df8 Bjorn Andersson 2025-04-14 775 ret = dwc3_core_probe(&probe_data);
2bc02355f8ba2c Lee Jones 2019-06-17 776 if (ret) {
1881a32fe14df8 Bjorn Andersson 2025-04-14 777 ret = dev_err_probe(dev, ret, "failed to register DWC3 Core\n");
41717b88abf1ca Krishna Kurapati 2024-03-05 778 goto clk_disable;
a4333c3a6ba9ca Manu Gautam 2018-05-09 779 }
a4333c3a6ba9ca Manu Gautam 2018-05-09 780
bea46b9815154a Sandeep Maheswaram 2020-07-27 781 ret = dwc3_qcom_interconnect_init(qcom);
bea46b9815154a Sandeep Maheswaram 2020-07-27 782 if (ret)
1881a32fe14df8 Bjorn Andersson 2025-04-14 783 goto remove_core;
bea46b9815154a Sandeep Maheswaram 2020-07-27 784
e3fafbd8e36530 Johan Hovold 2022-08-04 785 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source");
e3fafbd8e36530 Johan Hovold 2022-08-04 786 device_init_wakeup(&pdev->dev, wakeup_source);
d9be8d5c5b032e Sandeep Maheswaram 2022-06-13 787
a4333c3a6ba9ca Manu Gautam 2018-05-09 788 qcom->is_suspended = false;
a4333c3a6ba9ca Manu Gautam 2018-05-09 789
a4333c3a6ba9ca Manu Gautam 2018-05-09 790 return 0;
a4333c3a6ba9ca Manu Gautam 2018-05-09 791
1881a32fe14df8 Bjorn Andersson 2025-04-14 792 remove_core:
1881a32fe14df8 Bjorn Andersson 2025-04-14 793 dwc3_core_remove(&qcom->dwc);
a4333c3a6ba9ca Manu Gautam 2018-05-09 794 clk_disable:
e33ebb133a245a Bjorn Andersson 2025-05-08 795 clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
a4333c3a6ba9ca Manu Gautam 2018-05-09 796
79456073227880 Sriram Dash 2025-11-27 797 resources_off:
79456073227880 Sriram Dash 2025-11-27 798 if (qcom->fw_managed)
79456073227880 Sriram Dash 2025-11-27 799 dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT);
79456073227880 Sriram Dash 2025-11-27 800
a4333c3a6ba9ca Manu Gautam 2018-05-09 @801 return ret;
a4333c3a6ba9ca Manu Gautam 2018-05-09 802 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Thu, Nov 27, 2025 at 04:01:45PM +0530, Sriram Dash wrote:
> Add support for firmware-managed resource states in the
> Qualcomm DWC3 USB controller driver. On platforms
> like sa8255p, where controller resources are abstracted
> and managed collectively by firmware, the driver communicates
> power management transitions using dedicated resource state
> levels via dev_pm_opp_set_level().
>
> Macros are introduced to represent key lifecycle events:
> initialization, system and runtime suspend/resume, and exit.
> The driver sets the appropriate resource state during probe,
> remove, suspend, and resume operations, enabling bulk ON/OFF
> transitions of grouped resources according to the
> controller's operational state.
>
> Signed-off-by: Sriram Dash <sriram.dash@oss.qualcomm.com>
> Co-developed-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
> Signed-off-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 97 ++++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 88 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index 9ac75547820d..9615ca6cfcae 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -13,6 +13,8 @@
> #include <linux/kernel.h>
> #include <linux/interconnect.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_opp.h>
> #include <linux/phy/phy.h>
> #include <linux/usb/of.h>
> #include <linux/reset.h>
> @@ -85,10 +87,48 @@ struct dwc3_qcom {
> struct icc_path *icc_path_apps;
>
> enum usb_role current_role;
> + bool fw_managed;
> };
>
> #define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc)
>
> +/*
> + * QCOM DWC3 USB Controller: Firmware-Managed Resource State Levels
> + *
> + * On select Qualcomm platforms, the USB controller’s power-related
> + * resources including GDSC, reset lines, clocks, and interconnects
> + * are managed collectively by system firmware via SCMI. The driver
> + * signals the controller’s operational state to firmware using these
> + * levels, each mapped to a specific power management transition or
> + * lifecycle event:
> + *
> + * DWC3_QCOM_FW_MANAGED_INIT
Both power and performance states are typically...states...
But these are actions/transitions between states.
The purpose of doing firmware assisted resource management (like done in
ACPI) is that it abstracts away the power management aspects from the OS
implementation, here we instead seems to complicate the OS
implementation.
> + * Enable GDSC, Assert and Deassert Resets, and turn ON all clocks
> + * and interconnects.
> + *
> + * DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME
> + * Enable GDSC and turn ON all clocks and interconnects.
> + *
> + * DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME
> + * Turn ON all clocks and interconnects.
> + *
> + * DWC3_QCOM_FW_MANAGED_EXIT
> + * Turn OFF all clocks and interconnects, Assert reset and disable GDSC.
> + *
> + * DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND
> + * Turn OFF all clocks and interconnects and disable GDSC.
> + *
> + * DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND
> + * Turn OFF clocks and interconnects.
> + */
> +
> +#define DWC3_QCOM_FW_MANAGED_INIT 1
> +#define DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME 2
> +#define DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME 3
Given that dwc3_core_probe() calls pm_runtime_forbid(), do we actually
hit these states, or are you in practice only hitting some "D0" and "D3"
states?
Could this be simplified to match what we would need here for an ACPI
system?
Regards,
Bjorn
> +#define DWC3_QCOM_FW_MANAGED_EXIT 8
> +#define DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND 9
> +#define DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND 10
> +
> static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
> {
> u32 reg;
> @@ -335,7 +375,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
> dwc3_qcom_enable_port_interrupts(&qcom->ports[i]);
> }
>
> -static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> +static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup, pm_message_t msg)
> {
> u32 val;
> int i, ret;
> @@ -348,6 +388,13 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
> dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
> }
> + if (qcom->fw_managed) {
> + if (PMSG_IS_AUTO(msg))
> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND);
> + else
> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND);
> + }
> +
> clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
>
> ret = dwc3_qcom_interconnect_disable(qcom);
> @@ -369,7 +416,7 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> return 0;
> }
>
> -static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
> +static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup, pm_message_t msg)
> {
> int ret;
> int i;
> @@ -380,6 +427,18 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
> if (dwc3_qcom_is_host(qcom) && wakeup)
> dwc3_qcom_disable_interrupts(qcom);
>
> + if (qcom->fw_managed) {
> + if (PMSG_IS_AUTO(msg))
> + ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME);
> + else
> + ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME);
> +
> + if (ret < 0) {
> + dev_err(qcom->dev, "Failed to Resume fw managed device\n");
> + return ret;
> + }
> + }
> +
> ret = clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks);
> if (ret < 0)
> return ret;
> @@ -624,10 +683,18 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>
> qcom->dev = &pdev->dev;
>
> + qcom->fw_managed = device_get_match_data(dev);
> + if (qcom->fw_managed) {
> + ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_INIT);
> + if (ret < 0)
> + return ret;
> + }
> +
> qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
> if (IS_ERR(qcom->resets)) {
> - return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
> - "failed to get resets\n");
> + dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
> + "failed to get resets\n");
> + goto resources_off;
> }
>
> ret = devm_clk_bulk_get_all(&pdev->dev, &qcom->clks);
> @@ -638,7 +705,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> ret = reset_control_assert(qcom->resets);
> if (ret) {
> dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
> - return ret;
> + goto resources_off;
> }
>
> usleep_range(10, 1000);
> @@ -727,6 +794,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> clk_disable:
> clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
>
> +resources_off:
> + if (qcom->fw_managed)
> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT);
> +
> return ret;
> }
>
> @@ -739,6 +810,10 @@ static void dwc3_qcom_remove(struct platform_device *pdev)
> return;
>
> dwc3_core_remove(&qcom->dwc);
> +
> + if (qcom->fw_managed)
> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT);
> +
> clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
> dwc3_qcom_interconnect_exit(qcom);
>
> @@ -756,7 +831,7 @@ static int dwc3_qcom_pm_suspend(struct device *dev)
> if (ret)
> return ret;
>
> - ret = dwc3_qcom_suspend(qcom, wakeup);
> + ret = dwc3_qcom_suspend(qcom, wakeup, PMSG_SUSPEND);
> if (ret)
> return ret;
>
> @@ -772,7 +847,7 @@ static int dwc3_qcom_pm_resume(struct device *dev)
> bool wakeup = device_may_wakeup(dev);
> int ret;
>
> - ret = dwc3_qcom_resume(qcom, wakeup);
> + ret = dwc3_qcom_resume(qcom, wakeup, PMSG_RESUME);
> if (ret)
> return ret;
>
> @@ -809,7 +884,7 @@ static int dwc3_qcom_runtime_suspend(struct device *dev)
> if (ret)
> return ret;
>
> - return dwc3_qcom_suspend(qcom, true);
> + return dwc3_qcom_suspend(qcom, true, PMSG_AUTO_SUSPEND);
> }
>
> static int dwc3_qcom_runtime_resume(struct device *dev)
> @@ -818,7 +893,7 @@ static int dwc3_qcom_runtime_resume(struct device *dev)
> struct dwc3_qcom *qcom = to_dwc3_qcom(dwc);
> int ret;
>
> - ret = dwc3_qcom_resume(qcom, true);
> + ret = dwc3_qcom_resume(qcom, true, PMSG_AUTO_RESUME);
> if (ret)
> return ret;
>
> @@ -839,6 +914,10 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
> };
>
> static const struct of_device_id dwc3_qcom_of_match[] = {
> + {
> + .compatible = "qcom,snps-dwc3-fw-managed",
> + .data = (void *)true,
> + },
> { .compatible = "qcom,snps-dwc3" },
> { }
> };
>
> --
> 2.34.1
>
On 12/2/2025 10:51 AM, Bjorn Andersson wrote:
> On Thu, Nov 27, 2025 at 04:01:45PM +0530, Sriram Dash wrote:
>> Add support for firmware-managed resource states in the
>> Qualcomm DWC3 USB controller driver. On platforms
>> like sa8255p, where controller resources are abstracted
>> and managed collectively by firmware, the driver communicates
>> power management transitions using dedicated resource state
>> levels via dev_pm_opp_set_level().
>>
>> Macros are introduced to represent key lifecycle events:
>> initialization, system and runtime suspend/resume, and exit.
>> The driver sets the appropriate resource state during probe,
>> remove, suspend, and resume operations, enabling bulk ON/OFF
>> transitions of grouped resources according to the
>> controller's operational state.
>>
>> Signed-off-by: Sriram Dash <sriram.dash@oss.qualcomm.com>
>> Co-developed-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
>> Signed-off-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
>> ---
>> drivers/usb/dwc3/dwc3-qcom.c | 97 ++++++++++++++++++++++++++++++++++++++++----
>> 1 file changed, 88 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
>> index 9ac75547820d..9615ca6cfcae 100644
>> --- a/drivers/usb/dwc3/dwc3-qcom.c
>> +++ b/drivers/usb/dwc3/dwc3-qcom.c
>> @@ -13,6 +13,8 @@
>> #include <linux/kernel.h>
>> #include <linux/interconnect.h>
>> #include <linux/platform_device.h>
>> +#include <linux/pm_domain.h>
>> +#include <linux/pm_opp.h>
>> #include <linux/phy/phy.h>
>> #include <linux/usb/of.h>
>> #include <linux/reset.h>
>> @@ -85,10 +87,48 @@ struct dwc3_qcom {
>> struct icc_path *icc_path_apps;
>>
>> enum usb_role current_role;
>> + bool fw_managed;
>> };
>>
>> #define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc)
>>
>> +/*
>> + * QCOM DWC3 USB Controller: Firmware-Managed Resource State Levels
>> + *
>> + * On select Qualcomm platforms, the USB controller’s power-related
>> + * resources including GDSC, reset lines, clocks, and interconnects
>> + * are managed collectively by system firmware via SCMI. The driver
>> + * signals the controller’s operational state to firmware using these
>> + * levels, each mapped to a specific power management transition or
>> + * lifecycle event:
>> + *
>> + * DWC3_QCOM_FW_MANAGED_INIT
> Both power and performance states are typically...states...
> But these are actions/transitions between states.
>
>
> The purpose of doing firmware assisted resource management (like done in
> ACPI) is that it abstracts away the power management aspects from the OS
> implementation, here we instead seems to complicate the OS
> implementation.
>
>> + * Enable GDSC, Assert and Deassert Resets, and turn ON all clocks
>> + * and interconnects.
>> + *
>> + * DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME
>> + * Enable GDSC and turn ON all clocks and interconnects.
>> + *
>> + * DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME
>> + * Turn ON all clocks and interconnects.
>> + *
>> + * DWC3_QCOM_FW_MANAGED_EXIT
>> + * Turn OFF all clocks and interconnects, Assert reset and disable GDSC.
>> + *
>> + * DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND
>> + * Turn OFF all clocks and interconnects and disable GDSC.
>> + *
>> + * DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND
>> + * Turn OFF clocks and interconnects.
>> + */
>> +
>> +#define DWC3_QCOM_FW_MANAGED_INIT 1
>> +#define DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME 2
>> +#define DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME 3
> Given that dwc3_core_probe() calls pm_runtime_forbid(), do we actually
> hit these states, or are you in practice only hitting some "D0" and "D3"
> states?
>
> Could this be simplified to match what we would need here for an ACPI
> system?
Hi Bjorn,
thanks for the comments.
You’re right that the wording in the comment makes these look like
explicit “do X/Y/Z now” transitions rather than passive states. The
intention is not to expose an imperative sequence to firmware, but to
advertise a small set of abstract “resource configurations” that
correspond to specific OS power‑management contexts in the driver.
On sa8255p, the USB controller and its associated resources (GDSC,
clocks, interconnects, resets) are grouped behind a single
firmware‑managed perf domain. From the driver’s perspective we only have
a few meaningful configurations:
initial bring‑up during probe,
system suspend / system resume,
runtime suspend / runtime resume (planned once runtime PM is enabled), and
final shutdown on remove.
The levels are meant to encode which phase of the lifecycle we are in,
so that firmware can choose an internal representation that matches its
own notion of “D0‑like”, “temporarily suspended” or “off / removed”,
including any differences in how aggressively it can drop power, assert
resets, or preserve context.
You are correct that INIT and the various RESUME levels are all “on” in
the sense that the controller ends up operational, and similarly EXIT /
SUSPEND variants are “off / not actively used”. Today the driver does
not try to model these as strict D0/D3/D3hot/D3cold equivalents, because:
INIT may require a more complete bring‑up after boot, where firmware
might need to perform extra initialization compared to a resume from a
prior suspended state.
SYSTEM_* vs RUNTIME_* are tied to the OS‑level PM entry points
(dwc3_qcom_suspend() is used for both system and runtime suspend;
runtime is currently forbidden but it is planned later). The distinction
gives firmware the option to use different policies for system sleep vs
runtime idle, including wake‑capability and context‑retention.
That said, I agree that the current comment over‑specifies the concrete
actions (“Enable GDSC, Assert and Deassert Resets…”) and makes the
interface look more complicated than it actually is.
We can reword it to describe the effective resource state, without
prescribing exactly how the firmware should sequence GDSC, resets and
clocks. However, I’d still like to keep the separation between system
and runtime paths so that we don’t have to extend the protocol again
when runtime PM is enabled.
/*
* QCOM DWC3 USB Controller: Firmware-Managed Resource State Levels
*
* On select Qualcomm platforms, the USB controller’s power-related
* resources (such as GDSC, reset lines, clocks, and interconnects)
* are managed collectively by system firmware. The driver reports
* the controller’s lifecycle and power-management context using the
* following abstract resource state levels. The exact sequencing and
* choice of underlying resources for each level is left to firmware.
*
* DWC3_QCOM_FW_MANAGED_INIT
* Controller is initialized after probe and brought into a fully
* operational state suitable for normal use.
*
* DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME
* Controller returns from system suspend to a fully operational
* state suitable for normal use.
*
* DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME
* Controller returns from runtime suspend to an operational state
* sufficient for runtime activity.
*
* DWC3_QCOM_FW_MANAGED_EXIT
* Controller is shut down as part of driver removal and may be put
* into a fully powered-off state with no requirement for retention.
*
* DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND
* Controller is quiesced for system suspend; resources may be
* reduced or powered down according to platform policy.
*
* DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND
* Controller is quiesced for runtime suspend; a lower-power state
* is entered while allowing a later runtime resume.
*/
#define DWC3_QCOM_FW_MANAGED_INIT 1
#define DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME 2
#define DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME 3
#define DWC3_QCOM_FW_MANAGED_EXIT 8
#define DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND 9
#define DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND 10
Let me know if this is OK.
> Regards,
> Bjorn
>
>> +#define DWC3_QCOM_FW_MANAGED_EXIT 8
>> +#define DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND 9
>> +#define DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND 10
>> +
>> static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
>> {
>> u32 reg;
>> @@ -335,7 +375,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
>> dwc3_qcom_enable_port_interrupts(&qcom->ports[i]);
>> }
>>
>> -static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
>> +static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup, pm_message_t msg)
>> {
>> u32 val;
>> int i, ret;
>> @@ -348,6 +388,13 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
>> if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
>> dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
>> }
>> + if (qcom->fw_managed) {
>> + if (PMSG_IS_AUTO(msg))
>> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND);
>> + else
>> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND);
>> + }
>> +
>> clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
>>
>> ret = dwc3_qcom_interconnect_disable(qcom);
>> @@ -369,7 +416,7 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
>> return 0;
>> }
>>
>> -static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
>> +static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup, pm_message_t msg)
>> {
>> int ret;
>> int i;
>> @@ -380,6 +427,18 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
>> if (dwc3_qcom_is_host(qcom) && wakeup)
>> dwc3_qcom_disable_interrupts(qcom);
>>
>> + if (qcom->fw_managed) {
>> + if (PMSG_IS_AUTO(msg))
>> + ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME);
>> + else
>> + ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME);
>> +
>> + if (ret < 0) {
>> + dev_err(qcom->dev, "Failed to Resume fw managed device\n");
>> + return ret;
>> + }
>> + }
>> +
>> ret = clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks);
>> if (ret < 0)
>> return ret;
>> @@ -624,10 +683,18 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>>
>> qcom->dev = &pdev->dev;
>>
>> + qcom->fw_managed = device_get_match_data(dev);
>> + if (qcom->fw_managed) {
>> + ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_INIT);
>> + if (ret < 0)
>> + return ret;
>> + }
>> +
>> qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
>> if (IS_ERR(qcom->resets)) {
>> - return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
>> - "failed to get resets\n");
>> + dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
>> + "failed to get resets\n");
>> + goto resources_off;
>> }
>>
>> ret = devm_clk_bulk_get_all(&pdev->dev, &qcom->clks);
>> @@ -638,7 +705,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>> ret = reset_control_assert(qcom->resets);
>> if (ret) {
>> dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
>> - return ret;
>> + goto resources_off;
>> }
>>
>> usleep_range(10, 1000);
>> @@ -727,6 +794,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>> clk_disable:
>> clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
>>
>> +resources_off:
>> + if (qcom->fw_managed)
>> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT);
>> +
>> return ret;
>> }
>>
>> @@ -739,6 +810,10 @@ static void dwc3_qcom_remove(struct platform_device *pdev)
>> return;
>>
>> dwc3_core_remove(&qcom->dwc);
>> +
>> + if (qcom->fw_managed)
>> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT);
>> +
>> clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
>> dwc3_qcom_interconnect_exit(qcom);
>>
>> @@ -756,7 +831,7 @@ static int dwc3_qcom_pm_suspend(struct device *dev)
>> if (ret)
>> return ret;
>>
>> - ret = dwc3_qcom_suspend(qcom, wakeup);
>> + ret = dwc3_qcom_suspend(qcom, wakeup, PMSG_SUSPEND);
>> if (ret)
>> return ret;
>>
>> @@ -772,7 +847,7 @@ static int dwc3_qcom_pm_resume(struct device *dev)
>> bool wakeup = device_may_wakeup(dev);
>> int ret;
>>
>> - ret = dwc3_qcom_resume(qcom, wakeup);
>> + ret = dwc3_qcom_resume(qcom, wakeup, PMSG_RESUME);
>> if (ret)
>> return ret;
>>
>> @@ -809,7 +884,7 @@ static int dwc3_qcom_runtime_suspend(struct device *dev)
>> if (ret)
>> return ret;
>>
>> - return dwc3_qcom_suspend(qcom, true);
>> + return dwc3_qcom_suspend(qcom, true, PMSG_AUTO_SUSPEND);
>> }
>>
>> static int dwc3_qcom_runtime_resume(struct device *dev)
>> @@ -818,7 +893,7 @@ static int dwc3_qcom_runtime_resume(struct device *dev)
>> struct dwc3_qcom *qcom = to_dwc3_qcom(dwc);
>> int ret;
>>
>> - ret = dwc3_qcom_resume(qcom, true);
>> + ret = dwc3_qcom_resume(qcom, true, PMSG_AUTO_RESUME);
>> if (ret)
>> return ret;
>>
>> @@ -839,6 +914,10 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
>> };
>>
>> static const struct of_device_id dwc3_qcom_of_match[] = {
>> + {
>> + .compatible = "qcom,snps-dwc3-fw-managed",
>> + .data = (void *)true,
>> + },
>> { .compatible = "qcom,snps-dwc3" },
>> { }
>> };
>>
>> --
>> 2.34.1
>>
On Tue, Dec 02, 2025 at 12:07:01PM +0530, Sriram Dash wrote:
> On 12/2/2025 10:51 AM, Bjorn Andersson wrote:
> > On Thu, Nov 27, 2025 at 04:01:45PM +0530, Sriram Dash wrote:
> >> Add support for firmware-managed resource states in the
> >> Qualcomm DWC3 USB controller driver. On platforms
> >> like sa8255p, where controller resources are abstracted
> >> and managed collectively by firmware, the driver communicates
> >> power management transitions using dedicated resource state
> >> levels via dev_pm_opp_set_level().
> >>
> >> Macros are introduced to represent key lifecycle events:
> >> initialization, system and runtime suspend/resume, and exit.
> >> The driver sets the appropriate resource state during probe,
> >> remove, suspend, and resume operations, enabling bulk ON/OFF
> >> transitions of grouped resources according to the
> >> controller's operational state.
> >>
> >> Signed-off-by: Sriram Dash <sriram.dash@oss.qualcomm.com>
> >> Co-developed-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
> >> Signed-off-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
> >> ---
> >> drivers/usb/dwc3/dwc3-qcom.c | 97 ++++++++++++++++++++++++++++++++++++++++----
> >> 1 file changed, 88 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> >> index 9ac75547820d..9615ca6cfcae 100644
> >> --- a/drivers/usb/dwc3/dwc3-qcom.c
> >> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> >> @@ -13,6 +13,8 @@
> >> #include <linux/kernel.h>
> >> #include <linux/interconnect.h>
> >> #include <linux/platform_device.h>
> >> +#include <linux/pm_domain.h>
> >> +#include <linux/pm_opp.h>
> >> #include <linux/phy/phy.h>
> >> #include <linux/usb/of.h>
> >> #include <linux/reset.h>
> >> @@ -85,10 +87,48 @@ struct dwc3_qcom {
> >> struct icc_path *icc_path_apps;
> >>
> >> enum usb_role current_role;
> >> + bool fw_managed;
> >> };
> >>
> >> #define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc)
> >>
> >> +/*
> >> + * QCOM DWC3 USB Controller: Firmware-Managed Resource State Levels
> >> + *
> >> + * On select Qualcomm platforms, the USB controller’s power-related
> >> + * resources including GDSC, reset lines, clocks, and interconnects
> >> + * are managed collectively by system firmware via SCMI. The driver
> >> + * signals the controller’s operational state to firmware using these
> >> + * levels, each mapped to a specific power management transition or
> >> + * lifecycle event:
> >> + *
> >> + * DWC3_QCOM_FW_MANAGED_INIT
> > Both power and performance states are typically...states...
> > But these are actions/transitions between states.
> >
> >
> > The purpose of doing firmware assisted resource management (like done in
> > ACPI) is that it abstracts away the power management aspects from the OS
> > implementation, here we instead seems to complicate the OS
> > implementation.
> >
> >> + * Enable GDSC, Assert and Deassert Resets, and turn ON all clocks
> >> + * and interconnects.
> >> + *
> >> + * DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME
> >> + * Enable GDSC and turn ON all clocks and interconnects.
> >> + *
> >> + * DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME
> >> + * Turn ON all clocks and interconnects.
> >> + *
> >> + * DWC3_QCOM_FW_MANAGED_EXIT
> >> + * Turn OFF all clocks and interconnects, Assert reset and disable GDSC.
> >> + *
> >> + * DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND
> >> + * Turn OFF all clocks and interconnects and disable GDSC.
> >> + *
> >> + * DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND
> >> + * Turn OFF clocks and interconnects.
> >> + */
> >> +
> >> +#define DWC3_QCOM_FW_MANAGED_INIT 1
> >> +#define DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME 2
> >> +#define DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME 3
> > Given that dwc3_core_probe() calls pm_runtime_forbid(), do we actually
> > hit these states, or are you in practice only hitting some "D0" and "D3"
> > states?
> >
> > Could this be simplified to match what we would need here for an ACPI
> > system?
>
>
> Hi Bjorn,
>
> thanks for the comments.
>
> You’re right that the wording in the comment makes these look like
> explicit “do X/Y/Z now” transitions rather than passive states. The
> intention is not to expose an imperative sequence to firmware, but to
> advertise a small set of abstract “resource configurations” that
> correspond to specific OS power‑management contexts in the driver.
>
The problem I have is that when you talk about "states" here, you have
the Linux device's runtime and/or system state (active vs idle vs
suspended), or you're talking about the state of a clock, a regulator,
etc (on vs off, perhaps "on at X Hz"), or a performance state (such as 11).
But the states you're talking about is "the state of changing from
active to idle" (which in the other model is the edges between states).
> On sa8255p, the USB controller and its associated resources (GDSC,
> clocks, interconnects, resets) are grouped behind a single
> firmware‑managed perf domain. From the driver’s perspective we only have
> a few meaningful configurations:
>
> initial bring‑up during probe,
> system suspend / system resume,
> runtime suspend / runtime resume (planned once runtime PM is enabled), and
> final shutdown on remove.
>
> The levels are meant to encode which phase of the lifecycle we are in,
> so that firmware can choose an internal representation that matches its
> own notion of “D0‑like”, “temporarily suspended” or “off / removed”,
> including any differences in how aggressively it can drop power, assert
> resets, or preserve context.
>
> You are correct that INIT and the various RESUME levels are all “on” in
> the sense that the controller ends up operational, and similarly EXIT /
> SUSPEND variants are “off / not actively used”. Today the driver does
> not try to model these as strict D0/D3/D3hot/D3cold equivalents, because:
>
> INIT may require a more complete bring‑up after boot, where firmware
> might need to perform extra initialization compared to a resume from a
> prior suspended state.
But technically, the driver doesn't know what resource state we're in at
probe time. UEFI might have performed initialization already, it might
have turned the controller off, it might have left it in the shallow
state for some reason.
So it seems to me that exposing this as ON/OFF/"shallow-off" to the OS,
and then have the firmware track the state and perform the adequate
transition would be better.
> SYSTEM_* vs RUNTIME_* are tied to the OS‑level PM entry points
> (dwc3_qcom_suspend() is used for both system and runtime suspend;
> runtime is currently forbidden but it is planned later). The distinction
> gives firmware the option to use different policies for system sleep vs
> runtime idle, including wake‑capability and context‑retention.
The wake capability is an interesting topic, because this would
generally be considered a policy decision presented to the OS (to user
space inf act), not a decision encoded in the firmware. I'm not sure how
we would expose that decision through this interface.
> That said, I agree that the current comment over‑specifies the concrete
> actions (“Enable GDSC, Assert and Deassert Resets…”) and makes the
> interface look more complicated than it actually is.
>
I'm not concerned about the complexity of the operations abstracted away
by these signals, Linux has no expectations of the complexity of a
typical D3->D0 transition.
> We can reword it to describe the effective resource state, without
> prescribing exactly how the firmware should sequence GDSC, resets and
> clocks. However, I’d still like to keep the separation between system
> and runtime paths so that we don’t have to extend the protocol again
> when runtime PM is enabled.
>
> /*
> * QCOM DWC3 USB Controller: Firmware-Managed Resource State Levels
> *
> * On select Qualcomm platforms, the USB controller’s power-related
> * resources (such as GDSC, reset lines, clocks, and interconnects)
> * are managed collectively by system firmware. The driver reports
> * the controller’s lifecycle and power-management context using the
> * following abstract resource state levels. The exact sequencing and
> * choice of underlying resources for each level is left to firmware.
> *
> * DWC3_QCOM_FW_MANAGED_INIT
> * Controller is initialized after probe and brought into a fully
> * operational state suitable for normal use.
> *
> * DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME
> * Controller returns from system suspend to a fully operational
> * state suitable for normal use.
> *
> * DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME
> * Controller returns from runtime suspend to an operational state
> * sufficient for runtime activity.
> *
> * DWC3_QCOM_FW_MANAGED_EXIT
> * Controller is shut down as part of driver removal and may be put
> * into a fully powered-off state with no requirement for retention.
> *
> * DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND
> * Controller is quiesced for system suspend; resources may be
> * reduced or powered down according to platform policy.
> *
> * DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND
> * Controller is quiesced for runtime suspend; a lower-power state
> * is entered while allowing a later runtime resume.
> */
> #define DWC3_QCOM_FW_MANAGED_INIT 1
> #define DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME 2
> #define DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME 3
> #define DWC3_QCOM_FW_MANAGED_EXIT 8
> #define DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND 9
> #define DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND 10
>
>
> Let me know if this is OK.
My concern remains, that these are explained as "states", but once you
enter any of the states "init", "system_resume", or "runtime_resume" I
expect the hardware to be in some particular configuration (a state).
It is true that we're trying to convey the "state change" (an action) in
the Linux device's power model to the firmware, so I understand why
you're communicating an "action" in each step, but you're doing that by
taking a performance domain to a particular "state".
I.e. you're using the performance state selection as a messaging
mechanism.
Regards,
Bjorn
>
>
>
> > Regards,
> > Bjorn
> >
> >> +#define DWC3_QCOM_FW_MANAGED_EXIT 8
> >> +#define DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND 9
> >> +#define DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND 10
> >> +
> >> static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
> >> {
> >> u32 reg;
> >> @@ -335,7 +375,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
> >> dwc3_qcom_enable_port_interrupts(&qcom->ports[i]);
> >> }
> >>
> >> -static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> >> +static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup, pm_message_t msg)
> >> {
> >> u32 val;
> >> int i, ret;
> >> @@ -348,6 +388,13 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> >> if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
> >> dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
> >> }
> >> + if (qcom->fw_managed) {
> >> + if (PMSG_IS_AUTO(msg))
> >> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND);
> >> + else
> >> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND);
> >> + }
> >> +
> >> clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
> >>
> >> ret = dwc3_qcom_interconnect_disable(qcom);
> >> @@ -369,7 +416,7 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> >> return 0;
> >> }
> >>
> >> -static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
> >> +static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup, pm_message_t msg)
> >> {
> >> int ret;
> >> int i;
> >> @@ -380,6 +427,18 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
> >> if (dwc3_qcom_is_host(qcom) && wakeup)
> >> dwc3_qcom_disable_interrupts(qcom);
> >>
> >> + if (qcom->fw_managed) {
> >> + if (PMSG_IS_AUTO(msg))
> >> + ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME);
> >> + else
> >> + ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME);
> >> +
> >> + if (ret < 0) {
> >> + dev_err(qcom->dev, "Failed to Resume fw managed device\n");
> >> + return ret;
> >> + }
> >> + }
> >> +
> >> ret = clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks);
> >> if (ret < 0)
> >> return ret;
> >> @@ -624,10 +683,18 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> >>
> >> qcom->dev = &pdev->dev;
> >>
> >> + qcom->fw_managed = device_get_match_data(dev);
> >> + if (qcom->fw_managed) {
> >> + ret = dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_INIT);
> >> + if (ret < 0)
> >> + return ret;
> >> + }
> >> +
> >> qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
> >> if (IS_ERR(qcom->resets)) {
> >> - return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
> >> - "failed to get resets\n");
> >> + dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
> >> + "failed to get resets\n");
> >> + goto resources_off;
> >> }
> >>
> >> ret = devm_clk_bulk_get_all(&pdev->dev, &qcom->clks);
> >> @@ -638,7 +705,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> >> ret = reset_control_assert(qcom->resets);
> >> if (ret) {
> >> dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
> >> - return ret;
> >> + goto resources_off;
> >> }
> >>
> >> usleep_range(10, 1000);
> >> @@ -727,6 +794,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> >> clk_disable:
> >> clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
> >>
> >> +resources_off:
> >> + if (qcom->fw_managed)
> >> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT);
> >> +
> >> return ret;
> >> }
> >>
> >> @@ -739,6 +810,10 @@ static void dwc3_qcom_remove(struct platform_device *pdev)
> >> return;
> >>
> >> dwc3_core_remove(&qcom->dwc);
> >> +
> >> + if (qcom->fw_managed)
> >> + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT);
> >> +
> >> clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks);
> >> dwc3_qcom_interconnect_exit(qcom);
> >>
> >> @@ -756,7 +831,7 @@ static int dwc3_qcom_pm_suspend(struct device *dev)
> >> if (ret)
> >> return ret;
> >>
> >> - ret = dwc3_qcom_suspend(qcom, wakeup);
> >> + ret = dwc3_qcom_suspend(qcom, wakeup, PMSG_SUSPEND);
> >> if (ret)
> >> return ret;
> >>
> >> @@ -772,7 +847,7 @@ static int dwc3_qcom_pm_resume(struct device *dev)
> >> bool wakeup = device_may_wakeup(dev);
> >> int ret;
> >>
> >> - ret = dwc3_qcom_resume(qcom, wakeup);
> >> + ret = dwc3_qcom_resume(qcom, wakeup, PMSG_RESUME);
> >> if (ret)
> >> return ret;
> >>
> >> @@ -809,7 +884,7 @@ static int dwc3_qcom_runtime_suspend(struct device *dev)
> >> if (ret)
> >> return ret;
> >>
> >> - return dwc3_qcom_suspend(qcom, true);
> >> + return dwc3_qcom_suspend(qcom, true, PMSG_AUTO_SUSPEND);
> >> }
> >>
> >> static int dwc3_qcom_runtime_resume(struct device *dev)
> >> @@ -818,7 +893,7 @@ static int dwc3_qcom_runtime_resume(struct device *dev)
> >> struct dwc3_qcom *qcom = to_dwc3_qcom(dwc);
> >> int ret;
> >>
> >> - ret = dwc3_qcom_resume(qcom, true);
> >> + ret = dwc3_qcom_resume(qcom, true, PMSG_AUTO_RESUME);
> >> if (ret)
> >> return ret;
> >>
> >> @@ -839,6 +914,10 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
> >> };
> >>
> >> static const struct of_device_id dwc3_qcom_of_match[] = {
> >> + {
> >> + .compatible = "qcom,snps-dwc3-fw-managed",
> >> + .data = (void *)true,
> >> + },
> >> { .compatible = "qcom,snps-dwc3" },
> >> { }
> >> };
> >>
> >> --
> >> 2.34.1
> >>
On 27/11/2025 11:31, Sriram Dash wrote: > Add support for firmware-managed resource states in the > Qualcomm DWC3 USB controller driver. On platforms > like sa8255p, where controller resources are abstracted > and managed collectively by firmware, the driver communicates > power management transitions using dedicated resource state > levels via dev_pm_opp_set_level(). > > Macros are introduced to represent key lifecycle events: > initialization, system and runtime suspend/resume, and exit. > The driver sets the appropriate resource state during probe, > remove, suspend, and resume operations, enabling bulk ON/OFF > transitions of grouped resources according to the > controller's operational state. > > Signed-off-by: Sriram Dash <sriram.dash@oss.qualcomm.com> > Co-developed-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com> > Signed-off-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com> Messed order of tags. Please read carefully submitting patches, so you understand what you certify before you actually certify. Best regards, Krzysztof
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