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Thu, 27 Nov 2025 02:32:38 -0800 (PST) Received: from hu-sriramd-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7d15f457c38sm1479819b3a.54.2025.11.27.02.32.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 02:32:38 -0800 (PST) From: Sriram Dash Date: Thu, 27 Nov 2025 16:01:45 +0530 Subject: [PATCH 2/2] usb: dwc3: qcom: Support firmware-managed resource states for power management Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251127-controller_scmi_upstream-v1-2-38bcca513c28@oss.qualcomm.com> References: <20251127-controller_scmi_upstream-v1-0-38bcca513c28@oss.qualcomm.com> In-Reply-To: <20251127-controller_scmi_upstream-v1-0-38bcca513c28@oss.qualcomm.com> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Thinh Nguyen Cc: jack.pham@oss.qualcomm.com, faisal.hassan@oss.qualcomm.com, krishna.kurapati@oss.qualcomm.com, andersson@kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sriram Dash , Konrad Dybcio , Shazad Hussain X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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On platforms like sa8255p, where controller resources are abstracted and managed collectively by firmware, the driver communicates power management transitions using dedicated resource state levels via dev_pm_opp_set_level(). Macros are introduced to represent key lifecycle events: initialization, system and runtime suspend/resume, and exit. The driver sets the appropriate resource state during probe, remove, suspend, and resume operations, enabling bulk ON/OFF transitions of grouped resources according to the controller's operational state. Signed-off-by: Sriram Dash Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain --- drivers/usb/dwc3/dwc3-qcom.c | 97 ++++++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 88 insertions(+), 9 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 9ac75547820d..9615ca6cfcae 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -85,10 +87,48 @@ struct dwc3_qcom { struct icc_path *icc_path_apps; =20 enum usb_role current_role; + bool fw_managed; }; =20 #define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc) =20 +/* + * QCOM DWC3 USB Controller: Firmware-Managed Resource State Levels + * + * On select Qualcomm platforms, the USB controller=E2=80=99s power-related + * resources including GDSC, reset lines, clocks, and interconnects + * are managed collectively by system firmware via SCMI. The driver + * signals the controller=E2=80=99s operational state to firmware using th= ese + * levels, each mapped to a specific power management transition or + * lifecycle event: + * + * DWC3_QCOM_FW_MANAGED_INIT + * Enable GDSC, Assert and Deassert Resets, and turn ON all clocks + * and interconnects. + * + * DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME + * Enable GDSC and turn ON all clocks and interconnects. + * + * DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME + * Turn ON all clocks and interconnects. + * + * DWC3_QCOM_FW_MANAGED_EXIT + * Turn OFF all clocks and interconnects, Assert reset and disable GDSC. + * + * DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND + * Turn OFF all clocks and interconnects and disable GDSC. + * + * DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND + * Turn OFF clocks and interconnects. + */ + +#define DWC3_QCOM_FW_MANAGED_INIT 1 +#define DWC3_QCOM_FW_MANAGED_SYSTEM_RESUME 2 +#define DWC3_QCOM_FW_MANAGED_RUNTIME_RESUME 3 +#define DWC3_QCOM_FW_MANAGED_EXIT 8 +#define DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND 9 +#define DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND 10 + static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 v= al) { u32 reg; @@ -335,7 +375,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qco= m *qcom) dwc3_qcom_enable_port_interrupts(&qcom->ports[i]); } =20 -static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) +static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup, pm_messa= ge_t msg) { u32 val; int i, ret; @@ -348,6 +388,13 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, b= ool wakeup) if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1); } + if (qcom->fw_managed) { + if (PMSG_IS_AUTO(msg)) + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_SUSPEND); + else + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_SUSPEND); + } + clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); =20 ret =3D dwc3_qcom_interconnect_disable(qcom); @@ -369,7 +416,7 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bo= ol wakeup) return 0; } =20 -static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) +static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup, pm_messag= e_t msg) { int ret; int i; @@ -380,6 +427,18 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bo= ol wakeup) if (dwc3_qcom_is_host(qcom) && wakeup) dwc3_qcom_disable_interrupts(qcom); =20 + if (qcom->fw_managed) { + if (PMSG_IS_AUTO(msg)) + ret =3D dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_RUNTIME_RE= SUME); + else + ret =3D dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_SYSTEM_RES= UME); + + if (ret < 0) { + dev_err(qcom->dev, "Failed to Resume fw managed device\n"); + return ret; + } + } + ret =3D clk_bulk_prepare_enable(qcom->num_clocks, qcom->clks); if (ret < 0) return ret; @@ -624,10 +683,18 @@ static int dwc3_qcom_probe(struct platform_device *pd= ev) =20 qcom->dev =3D &pdev->dev; =20 + qcom->fw_managed =3D device_get_match_data(dev); + if (qcom->fw_managed) { + ret =3D dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_INIT); + if (ret < 0) + return ret; + } + qcom->resets =3D devm_reset_control_array_get_optional_exclusive(dev); if (IS_ERR(qcom->resets)) { - return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), - "failed to get resets\n"); + dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), + "failed to get resets\n"); + goto resources_off; } =20 ret =3D devm_clk_bulk_get_all(&pdev->dev, &qcom->clks); @@ -638,7 +705,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev) ret =3D reset_control_assert(qcom->resets); if (ret) { dev_err(&pdev->dev, "failed to assert resets, err=3D%d\n", ret); - return ret; + goto resources_off; } =20 usleep_range(10, 1000); @@ -727,6 +794,10 @@ static int dwc3_qcom_probe(struct platform_device *pde= v) clk_disable: clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); =20 +resources_off: + if (qcom->fw_managed) + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT); + return ret; } =20 @@ -739,6 +810,10 @@ static void dwc3_qcom_remove(struct platform_device *p= dev) return; =20 dwc3_core_remove(&qcom->dwc); + + if (qcom->fw_managed) + dev_pm_opp_set_level(qcom->dev, DWC3_QCOM_FW_MANAGED_EXIT); + clk_bulk_disable_unprepare(qcom->num_clocks, qcom->clks); dwc3_qcom_interconnect_exit(qcom); =20 @@ -756,7 +831,7 @@ static int dwc3_qcom_pm_suspend(struct device *dev) if (ret) return ret; =20 - ret =3D dwc3_qcom_suspend(qcom, wakeup); + ret =3D dwc3_qcom_suspend(qcom, wakeup, PMSG_SUSPEND); if (ret) return ret; =20 @@ -772,7 +847,7 @@ static int dwc3_qcom_pm_resume(struct device *dev) bool wakeup =3D device_may_wakeup(dev); int ret; =20 - ret =3D dwc3_qcom_resume(qcom, wakeup); + ret =3D dwc3_qcom_resume(qcom, wakeup, PMSG_RESUME); if (ret) return ret; =20 @@ -809,7 +884,7 @@ static int dwc3_qcom_runtime_suspend(struct device *dev) if (ret) return ret; =20 - return dwc3_qcom_suspend(qcom, true); + return dwc3_qcom_suspend(qcom, true, PMSG_AUTO_SUSPEND); } =20 static int dwc3_qcom_runtime_resume(struct device *dev) @@ -818,7 +893,7 @@ static int dwc3_qcom_runtime_resume(struct device *dev) struct dwc3_qcom *qcom =3D to_dwc3_qcom(dwc); int ret; =20 - ret =3D dwc3_qcom_resume(qcom, true); + ret =3D dwc3_qcom_resume(qcom, true, PMSG_AUTO_RESUME); if (ret) return ret; =20 @@ -839,6 +914,10 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = =3D { }; =20 static const struct of_device_id dwc3_qcom_of_match[] =3D { + { + .compatible =3D "qcom,snps-dwc3-fw-managed", + .data =3D (void *)true, + }, { .compatible =3D "qcom,snps-dwc3" }, { } }; --=20 2.34.1