The S32G SoC family has 2 PCIe controllers based on Designware IP.
Add the support for Host mode.
Change since v5:
- Removed relocatable bit in yaml
- Dropped pcie-nxp-s32g-regs.h and moved reg definition in pcie-nxp-s32g.c
- Removed a useless ret
- Change kconfig from tri to bool because of memblock_start_of_DRAM()
Change since v4:
- Moved allof position and added interrupt-names' restriction in yaml file
- Removed PCIE_S32G_PE0_LINK_DBG_2 and instead use PCIE_PORT_DEBUG0|1
after receiving confirmation that they are the same.
Change since v3:
- Added Root Port node and reorder irq in binding
- Added Root Port management in driver
- Fix Kconfig PCIE_NXP_S32G position
- Use default pme_turn_off method
- Use ops->init() to simplify init and suspend/resume sequence
- Fix some typos.
- Removed MPS and ERROR config. Let core code configs them.
- Removed s32g_pcie_disable_equalization() from internal team request
- Removed dw_pcie_link_up() from suspend/resume functions with [1]
- I'm still waiting feedback from internal team before removing
.get_ltssm() and .link_up() functions.
[1] https://lore.kernel.org/all/20251107044319.8356-1-manivannan.sadhasivam@oss.qualcomm.com/
Change since v2:
- More cleanup on DT binding to comply with schemas/pci/snps,dw-pcie.yaml
- Added new reg and bit fields in pcie-designware.h
- Rename Kconfig PCIE_NXP_S32G and files to use pcie-nxp-s32g prefix
- Prefixed s32G registers with PCIE_S32G_ and use generic regs otherwise
- Use memblock_start_of_DRAM to set coherency boundary and add comments
- Fixed suspend/resume sequence by adding missing pme_turn_off function
- Added .probe_type = PROBE_PREFER_ASYNCHRONOUS to speedup probe
- Added pm_runtime_no_callbacks() as device doesn't have runtime ops
- Use writel/readl in ctrl function instead of dw_pcie_write/read
- Move Maintainer section in a dedicated entry
Change since v1:
- Cleanup DT binding
- Removed useless description and fixed typo, naming and indentation.
- Removed nxp,phy-mode binding until we agreed on a generic binding.
Default (crnss) mode is used for now. Generic binding wil be discussed
in a separate patch.
- Removed max-link-speed and num-lanes which are coming from
snps,dw-pcie-common.yaml. They are needed only if to restrict from the
the default hw config.
- Added unevaluatedProperties: false
- Keep Phys in host node until dw support Root Port node.
- Removed nxp-s32g-pcie-phy-submode.h until there is a generic clock and
spectrum binding.
- Rename files to start with pcie-s32g instead of pci-s32g
- Cleanup pcie-s32-reg.h and use dw_pcie_find_capability()
- cleanup and rename in s32g-pcie.c in addtion to remove useless check or
duplicate code.
- dw_pcie_suspend/resume_noirq() doesn't woork, need to set child device
to reach lowest state.
- Added L: imx@lists.linux.dev in MAINTAINERS
Vincent Guittot (4):
dt-bindings: PCI: s32g: Add NXP PCIe controller
PCI: dw: Add more registers and bitfield definition
PCI: s32g: Add initial PCIe support (RC)
MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver
.../bindings/pci/nxp,s32g-pcie.yaml | 130 ++++++
MAINTAINERS | 9 +
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-designware.h | 8 +
drivers/pci/controller/dwc/pcie-nxp-s32g.c | 404 ++++++++++++++++++
6 files changed, 562 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-nxp-s32g.c
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2.43.0