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[PATCH net-next 06/11] net: dsa: rzn1-a5psw: Add support for optional timestamp clock

Prabhakar posted 11 patches 1 week, 3 days ago
[PATCH net-next 06/11] net: dsa: rzn1-a5psw: Add support for optional timestamp clock
Posted by Prabhakar 1 week, 3 days ago 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add support for an optional "ts" (timestamp) clock to the RZN1 A5PSW
driver. Some SoC variants provide a dedicated clock source for
timestamping or time synchronization features within the Ethernet
switch IP.

Request and enable this clock during probe if defined in the device tree.
If the clock is not present, the driver continues to operate normally.

This change prepares the driver for Renesas RZ/T2H and RZ/N2H SoCs, where
the Ethernet switch includes a timestamp clock input.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/net/dsa/rzn1_a5psw.c | 7 +++++++
 drivers/net/dsa/rzn1_a5psw.h | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/net/dsa/rzn1_a5psw.c b/drivers/net/dsa/rzn1_a5psw.c
index 7b84585a5415..99098bc06efe 100644
--- a/drivers/net/dsa/rzn1_a5psw.c
+++ b/drivers/net/dsa/rzn1_a5psw.c
@@ -1243,6 +1243,13 @@ static int a5psw_probe(struct platform_device *pdev)
 		goto free_pcs;
 	}
 
+	a5psw->ts = devm_clk_get_optional_enabled(dev, "ts");
+	if (IS_ERR(a5psw->ts)) {
+		dev_err(dev, "failed get ts clock\n");
+		ret = PTR_ERR(a5psw->ts);
+		goto free_pcs;
+	}
+
 	reset = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
 	if (IS_ERR(reset)) {
 		ret = PTR_ERR(reset);
diff --git a/drivers/net/dsa/rzn1_a5psw.h b/drivers/net/dsa/rzn1_a5psw.h
index d54acedac194..81be30d6c55f 100644
--- a/drivers/net/dsa/rzn1_a5psw.h
+++ b/drivers/net/dsa/rzn1_a5psw.h
@@ -236,6 +236,7 @@ union lk_data {
  * @base: Base address of the switch
  * @hclk: hclk_switch clock
  * @clk: clk_switch clock
+ * @ts: Timestamp clock
  * @dev: Device associated to the switch
  * @mii_bus: MDIO bus struct
  * @mdio_freq: MDIO bus frequency requested
@@ -251,6 +252,7 @@ struct a5psw {
 	void __iomem *base;
 	struct clk *hclk;
 	struct clk *clk;
+	struct clk *ts;
 	struct device *dev;
 	struct mii_bus	*mii_bus;
 	struct phylink_pcs *pcs[A5PSW_PORTS_NUM - 1];
-- 
2.52.0
Re: [PATCH net-next 06/11] net: dsa: rzn1-a5psw: Add support for optional timestamp clock
Posted by Geert Uytterhoeven 1 week ago 
Hi Prabhakar,

On Fri, 21 Nov 2025 at 12:36, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add support for an optional "ts" (timestamp) clock to the RZN1 A5PSW
> driver. Some SoC variants provide a dedicated clock source for
> timestamping or time synchronization features within the Ethernet
> switch IP.
>
> Request and enable this clock during probe if defined in the device tree.
> If the clock is not present, the driver continues to operate normally.
>
> This change prepares the driver for Renesas RZ/T2H and RZ/N2H SoCs, where
> the Ethernet switch includes a timestamp clock input.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!


> --- a/drivers/net/dsa/rzn1_a5psw.c
> +++ b/drivers/net/dsa/rzn1_a5psw.c
> @@ -1243,6 +1243,13 @@ static int a5psw_probe(struct platform_device *pdev)
>                 goto free_pcs;
>         }
>
> +       a5psw->ts = devm_clk_get_optional_enabled(dev, "ts");
> +       if (IS_ERR(a5psw->ts)) {
> +               dev_err(dev, "failed get ts clock\n");

I think the error can be -EPROBE_DEFER, so this should use
dev_err_probe() instead. Same for the existing calls.

> +               ret = PTR_ERR(a5psw->ts);
> +               goto free_pcs;
> +       }
> +
>         reset = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
>         if (IS_ERR(reset)) {
>                 ret = PTR_ERR(reset);

> --- a/drivers/net/dsa/rzn1_a5psw.h
> +++ b/drivers/net/dsa/rzn1_a5psw.h
> @@ -236,6 +236,7 @@ union lk_data {
>   * @base: Base address of the switch
>   * @hclk: hclk_switch clock
>   * @clk: clk_switch clock
> + * @ts: Timestamp clock
>   * @dev: Device associated to the switch
>   * @mii_bus: MDIO bus struct
>   * @mdio_freq: MDIO bus frequency requested
> @@ -251,6 +252,7 @@ struct a5psw {
>         void __iomem *base;
>         struct clk *hclk;
>         struct clk *clk;
> +       struct clk *ts;

"ts" is only used inside a5psw_probe(), so it can be a local variable.

>         struct device *dev;
>         struct mii_bus  *mii_bus;
>         struct phylink_pcs *pcs[A5PSW_PORTS_NUM - 1];

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Re: [PATCH net-next 06/11] net: dsa: rzn1-a5psw: Add support for optional timestamp clock
Posted by Lad, Prabhakar 5 days, 7 hours ago 
Hi Geert,

Thank you for the review.

On Mon, Nov 24, 2025 at 12:45 PM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, 21 Nov 2025 at 12:36, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add support for an optional "ts" (timestamp) clock to the RZN1 A5PSW
> > driver. Some SoC variants provide a dedicated clock source for
> > timestamping or time synchronization features within the Ethernet
> > switch IP.
> >
> > Request and enable this clock during probe if defined in the device tree.
> > If the clock is not present, the driver continues to operate normally.
> >
> > This change prepares the driver for Renesas RZ/T2H and RZ/N2H SoCs, where
> > the Ethernet switch includes a timestamp clock input.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
>
> > --- a/drivers/net/dsa/rzn1_a5psw.c
> > +++ b/drivers/net/dsa/rzn1_a5psw.c
> > @@ -1243,6 +1243,13 @@ static int a5psw_probe(struct platform_device *pdev)
> >                 goto free_pcs;
> >         }
> >
> > +       a5psw->ts = devm_clk_get_optional_enabled(dev, "ts");
> > +       if (IS_ERR(a5psw->ts)) {
> > +               dev_err(dev, "failed get ts clock\n");
>
> I think the error can be -EPROBE_DEFER, so this should use
> dev_err_probe() instead. Same for the existing calls.
>
Agreed. For the existing calls I'll create a separate patch.

> > +               ret = PTR_ERR(a5psw->ts);
> > +               goto free_pcs;
> > +       }
> > +
> >         reset = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
> >         if (IS_ERR(reset)) {
> >                 ret = PTR_ERR(reset);
>
> > --- a/drivers/net/dsa/rzn1_a5psw.h
> > +++ b/drivers/net/dsa/rzn1_a5psw.h
> > @@ -236,6 +236,7 @@ union lk_data {
> >   * @base: Base address of the switch
> >   * @hclk: hclk_switch clock
> >   * @clk: clk_switch clock
> > + * @ts: Timestamp clock
> >   * @dev: Device associated to the switch
> >   * @mii_bus: MDIO bus struct
> >   * @mdio_freq: MDIO bus frequency requested
> > @@ -251,6 +252,7 @@ struct a5psw {
> >         void __iomem *base;
> >         struct clk *hclk;
> >         struct clk *clk;
> > +       struct clk *ts;
>
> "ts" is only used inside a5psw_probe(), so it can be a local variable.
>
Agreed, I will create a local variable.

Cheers,
Prabhakar

> >         struct device *dev;
> >         struct mii_bus  *mii_bus;
> >         struct phylink_pcs *pcs[A5PSW_PORTS_NUM - 1];
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
Re: [PATCH net-next 06/11] net: dsa: rzn1-a5psw: Add support for optional timestamp clock
Posted by Vladimir Oltean 1 week, 3 days ago 
On Fri, Nov 21, 2025 at 11:35:32AM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add support for an optional "ts" (timestamp) clock to the RZN1 A5PSW
> driver. Some SoC variants provide a dedicated clock source for
> timestamping or time synchronization features within the Ethernet
> switch IP.
> 
> Request and enable this clock during probe if defined in the device tree.
> If the clock is not present, the driver continues to operate normally.
> 
> This change prepares the driver for Renesas RZ/T2H and RZ/N2H SoCs, where
> the Ethernet switch includes a timestamp clock input.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---

What is the impact to the current driver if you get the clock and
disable it? I'm trying to understand if it's possible to only enable it
when using a feature that requires it.
Re: [PATCH net-next 06/11] net: dsa: rzn1-a5psw: Add support for optional timestamp clock
Posted by Lad, Prabhakar 5 days, 7 hours ago 
Hi Vladimir,

Thank you for the review.

On Fri, Nov 21, 2025 at 7:39 PM Vladimir Oltean <olteanv@gmail.com> wrote:
>
> On Fri, Nov 21, 2025 at 11:35:32AM +0000, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add support for an optional "ts" (timestamp) clock to the RZN1 A5PSW
> > driver. Some SoC variants provide a dedicated clock source for
> > timestamping or time synchronization features within the Ethernet
> > switch IP.
> >
> > Request and enable this clock during probe if defined in the device tree.
> > If the clock is not present, the driver continues to operate normally.
> >
> > This change prepares the driver for Renesas RZ/T2H and RZ/N2H SoCs, where
> > the Ethernet switch includes a timestamp clock input.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
>
> What is the impact to the current driver if you get the clock and
> disable it? I'm trying to understand if it's possible to only enable it
> when using a feature that requires it.
I actually cannot test this by disabling the clock. As the clock for
TS is coming from the core clock which is always ON and we dont have
control for the ON/OFF for it.

Cheers,
Prabhakar

Patchew 2.1-devel-b67e4c2

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