On 11/24/2025 5:46 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Fri 21 Nov 2025 at 18:59, Jian Hu <jian.hu@amlogic.com> wrote:
>
>> It introduces three clock controllers:
>> - SCMI clock controller: these clocks are managed by the SCP and handled through SCMI.
>> - PLL clock controller.
>> - peripheral clock controller.
>>
>> Changes v5 since v4 at [4]:
>> - rename rtc and cec dualdiv clocks
>> - rename dsp clocks
>> - rename anakin clocks
>> - rename fdiv2_divn to 25m and fix its parent
>> - add flag for T7_COMP_GATE
>> - use T7_COMP_SEL/DIV/GATE to define glitch clocks
>> - add CLK_SET_RATE_NO_REPARENT for t7_eth_rmii_sel and rtc
>> - move module_platform_driver after clock driver
> Looks good to me, just a few minor comments.
>
> It is too late of this cycle. Please check the comments and re-send on
> the next -rc1
Okay, I will address the comments and send v6 patch for the next -rc1.
Thanks for your review!
>
>> Changes v4 since v3 at [3]:
>> - drop amlogic_t7_pll_probe, use meson_clkc_mmio_probe instead
>> - add CLK_DIVIDER_MAX_AT_ZERO for pcie_pll_od clk
>> - add frac for hifi_dco_pll_dco
>> - add l_detect for mclk_pll_dco
>> - drop v3 5/6 patch, and use MESON_PCLK
>> - drop SPI_PWM_CLK_XX macro and use MESON_COMP_XX
>> - drop the register's prefix
>>
>> Changes v3 since v2 at [2]:
>> - update T7 PLL YAML
>> - add 't7_' prefix for t7 clock name and variable in t7-pll.c and t7-peripherals.c
>> - correct v1 patch link
>> - add new macro MESON_PCLK_V2
>> - update the driver,header,yaml file license
>>
>> Changes v2 since v1 at [1]:
>> - add CLK_MESON import
>> - add const for clkc_regmap_config in PLL driver
>> - fix eth_rmii_sel parent
>> - update T7 PLL YAML file
>>
>> [1]: https://lore.kernel.org/all/20241231060047.2298871-1-jian.hu@amlogic.com
>> [2]: https://lore.kernel.org/all/20250108094025.2664201-1-jian.hu@amlogic.com
>> [3]: https://lore.kernel.org/all/20250509074825.1933254-1-jian.hu@amlogic.com
>> [4]: https://lore.kernel.org/all/20251030094345.2571222-1-jian.hu@amlogic.com
>> Jian Hu (5):
>> dt-bindings: clock: add Amlogic T7 PLL clock controller
>> dt-bindings: clock: add Amlogic T7 SCMI clock controller
>> dt-bindings: clock: add Amlogic T7 peripherals clock controller
>> clk: meson: t7: add support for the T7 SoC PLL clock
>> clk: meson: t7: add t7 clock peripherals controller driver
>>
>> .../clock/amlogic,t7-peripherals-clkc.yaml | 116 ++
>> .../bindings/clock/amlogic,t7-pll-clkc.yaml | 114 ++
>> drivers/clk/meson/Kconfig | 27 +
>> drivers/clk/meson/Makefile | 2 +
>> drivers/clk/meson/t7-peripherals.c | 1266 +++++++++++++++++
>> drivers/clk/meson/t7-pll.c | 1068 ++++++++++++++
>> .../clock/amlogic,t7-peripherals-clkc.h | 228 +++
>> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 56 +
>> include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +
>> 9 files changed, 2924 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> create mode 100644 drivers/clk/meson/t7-peripherals.c
>> create mode 100644 drivers/clk/meson/t7-pll.c
>> create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
>> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>> create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
> --
> Jerome