From nobody Tue Dec 2 01:28:36 2025 Received: from mail-sh.amlogic.com (unknown [114.94.151.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D446348456; Fri, 21 Nov 2025 11:14:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.94.151.114 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763723696; cv=none; b=UblnzOWF+dtObWK2nsx/7QAA2EKog8KSxXdCkRIUmS/n3e3osWx1FVFL5LBx2yQ/YIx+uJoh9PUXw0P99suhOMQwTEIgJzTRLvMnlip4ANR2/yakFf3ZyNTR+zHVZ9sSUQsLCK00BlF0YUF5r6qb54No5iiOUWlOB+so5W3uX/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763723696; c=relaxed/simple; bh=E5igYXBmCyNyaq/a26aueEflhZpCWAta5CLO4LkMre8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Tu6OXHH7Was0HrYOWb8aQuPEEUqrsHwdfyJVlME9JZSXVezzdHbJjdy+3CL3cGFEEqAzXk8pw/ImQMu6LeI+FuN8yGf+prGSb8Hx1WPMQMQ8eRGLZKYp/dJqbJczBLBrTJe/cpyWEoqHfhgmL3+Myx2MEau+P4th8QauzqtMu7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=114.94.151.114 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.61; Fri, 21 Nov 2025 18:59:40 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , Conor Dooley , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH v5 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller Date: Fri, 21 Nov 2025 18:59:30 +0800 Message-ID: <20251121105934.1759745-2-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251121105934.1759745-1-jian.hu@amlogic.com> References: <20251121105934.1759745-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu Reviewed-by: Conor Dooley --- .../bindings/clock/amlogic,t7-pll-clkc.yaml | 114 ++++++++++++++++++ .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 56 +++++++++ 2 files changed, 170 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-= clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml new file mode 100644 index 000000000000..49c61f65deff --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T7 PLL Clock Control Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Jian Hu + - Xianwei Zhao + +properties: + compatible: + enum: + - amlogic,t7-gp0-pll + - amlogic,t7-gp1-pll + - amlogic,t7-hifi-pll + - amlogic,t7-pcie-pll + - amlogic,t7-mpll + - amlogic,t7-hdmi-pll + - amlogic,t7-mclk-pll + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: mclk pll input oscillator gate + - description: oscillator input clock source for mclk_sel_0 + - description: fixed input clock source for mclk_sel_0 + minItems: 1 + + clock-names: + items: + - const: in0 + - const: in1 + - const: in2 + minItems: 1 + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + const: amlogic,t7-mclk-pll + + then: + properties: + clocks: + minItems: 3 + + clock-names: + minItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - amlogic,t7-gp0-pll + - amlogic,t7-gp1--pll + - amlogic,t7-hifi-pll + - amlogic,t7-pcie-pll + - amlogic,t7-mpll + - amlogic,t7-hdmi-pll + + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@8080 { + compatible =3D "amlogic,t7-gp0-pll"; + reg =3D <0 0x8080 0 0x20>; + clocks =3D <&scmi_clk 2>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + clock-controller@8300 { + compatible =3D "amlogic,t7-mclk-pll"; + reg =3D <0 0x8300 0 0x18>; + clocks =3D <&scmi_clk 2>, + <&xtal>, + <&scmi_clk 31>; + clock-names =3D "in0", "in1", "in2"; + #clock-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-b= indings/clock/amlogic,t7-pll-clkc.h new file mode 100644 index 000000000000..e2481f2f1163 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved + */ + +#ifndef __T7_PLL_CLKC_H +#define __T7_PLL_CLKC_H + +/* GP0 */ +#define CLKID_GP0_PLL_DCO 0 +#define CLKID_GP0_PLL 1 + +/* GP1 */ +#define CLKID_GP1_PLL_DCO 0 +#define CLKID_GP1_PLL 1 + +/* HIFI */ +#define CLKID_HIFI_PLL_DCO 0 +#define CLKID_HIFI_PLL 1 + +/* PCIE */ +#define CLKID_PCIE_PLL_DCO 0 +#define CLKID_PCIE_PLL_DCO_DIV2 1 +#define CLKID_PCIE_PLL_OD 2 +#define CLKID_PCIE_PLL 3 + +/* MPLL */ +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 + +/* HDMI */ +#define CLKID_HDMI_PLL_DCO 0 +#define CLKID_HDMI_PLL_OD 1 +#define CLKID_HDMI_PLL 2 + +/* MCLK */ +#define CLKID_MCLK_PLL_DCO 0 +#define CLKID_MCLK_PRE 1 +#define CLKID_MCLK_PLL 2 +#define CLKID_MCLK_0_SEL 3 +#define CLKID_MCLK_0_DIV2 4 +#define CLKID_MCLK_0_PRE 5 +#define CLKID_MCLK_0 6 +#define CLKID_MCLK_1_SEL 7 +#define CLKID_MCLK_1_DIV2 8 +#define CLKID_MCLK_1_PRE 9 +#define CLKID_MCLK_1 10 + +#endif /* __T7_PLL_CLKC_H */ --=20 2.47.1 From nobody Tue Dec 2 01:28:36 2025 Received: from mail-sh.amlogic.com (unknown [114.94.151.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54B3F349B18; Fri, 21 Nov 2025 11:14:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.94.151.114 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763723698; cv=none; b=ZWxwdzXnEXL8Hp7jZNNXaecy00yvZ2ErMAfYMb/nNnovhx5bh2qWIZPYSKR57P258XZjaQEd9H1kmuRT5FX4Nd+SmRYWP4lOqBttSutRmKKZCcIMTlkBuyYi4XmRUYUkuKW5jT3U/1TpOejDqGwgfpSA4StGmQ+u2XtJcaMVfrU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763723698; c=relaxed/simple; bh=af0hA+zDPfoVkn9NLrQS1MdvE2XtFzvsEH809sbGmfg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FmEJov2Q+2W6++doAmcQJG4fDZgOJRpWMHBlpt5+aNZKbtcJijimJYZ+c4tM8zfhk9noH2+zUGdnelG2+U1MRMJps2NP2wdTm+ilJH5Xr9PfNbWh0GC8cDiNB2SddHF2F9Qr5CXcHyjbip6tLTHZblOOHLT/fVzorq8OI7Z24Io= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=114.94.151.114 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.61; Fri, 21 Nov 2025 18:59:41 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH v5 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller Date: Fri, 21 Nov 2025 18:59:31 +0800 Message-ID: <20251121105934.1759745-3-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251121105934.1759745-1-jian.hu@amlogic.com> References: <20251121105934.1759745-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu Acked-by: Rob Herring (Arm) --- include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h diff --git a/include/dt-bindings/clock/amlogic,t7-scmi.h b/include/dt-bindi= ngs/clock/amlogic,t7-scmi.h new file mode 100644 index 000000000000..27bd257bd4ea --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-scmi.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved + */ + +#ifndef __T7_SCMI_CLKC_H +#define __T7_SCMI_CLKC_H + +#define CLKID_DDR_PLL_OSC 0 +#define CLKID_AUD_PLL_OSC 1 +#define CLKID_TOP_PLL_OSC 2 +#define CLKID_TCON_PLL_OSC 3 +#define CLKID_USB_PLL0_OSC 4 +#define CLKID_USB_PLL1_OSC 5 +#define CLKID_MCLK_PLL_OSC 6 +#define CLKID_PCIE_OSC 7 +#define CLKID_ETH_PLL_OSC 8 +#define CLKID_PCIE_REFCLK_PLL_OSC 9 +#define CLKID_EARC_OSC 10 +#define CLKID_SYS1_PLL_OSC 11 +#define CLKID_HDMI_PLL_OSC 12 +#define CLKID_SYS_CLK 13 +#define CLKID_AXI_CLK 14 +#define CLKID_FIXED_PLL_DCO 15 +#define CLKID_FIXED_PLL 16 +#define CLKID_FCLK_DIV2_DIV 17 +#define CLKID_FCLK_DIV2 18 +#define CLKID_FCLK_DIV2P5_DIV 19 +#define CLKID_FCLK_DIV2P5 20 +#define CLKID_FCLK_DIV3_DIV 21 +#define CLKID_FCLK_DIV3 22 +#define CLKID_FCLK_DIV4_DIV 23 +#define CLKID_FCLK_DIV4 24 +#define CLKID_FCLK_DIV5_DIV 25 +#define CLKID_FCLK_DIV5 26 +#define CLKID_FCLK_DIV7_DIV 27 +#define CLKID_FCLK_DIV7 28 +#define CLKID_FCLK_50M_DIV 29 +#define CLKID_FCLK_50M 30 +#define CLKID_CPU_CLK 31 +#define CLKID_A73_CLK 32 +#define CLKID_CPU_CLK_DIV16_DIV 33 +#define CLKID_CPU_CLK_DIV16 34 +#define CLKID_A73_CLK_DIV16_DIV 35 +#define CLKID_A73_CLK_DIV16 36 + +#endif /* __T7_SCMI_CLKC_H */ --=20 2.47.1 From nobody Tue Dec 2 01:28:36 2025 Received: from mail-sh.amlogic.com (unknown [114.94.151.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 655E4346772; Fri, 21 Nov 2025 11:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.94.151.114 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763722860; cv=none; b=Q1ygxTCF3+Z8kelVxNgaIJRxji01xUI4+qXI4+ZV3VQlyoHGI6P9Hx/Yzec2//zoDgN+BH+iaVJ4JI4JUaKJYm0bXuH65fkAsNDzDLJzbQUhffBVA2Fm31vQJzN/f3rs7JF7NWnHZw48m8k3XdBqrAaoVHpS6GYz6HMqxSIb914= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763722860; c=relaxed/simple; bh=DusKfrc3K7uxkJ76mJMFQrjl7ZqTkpeNppuFqy6qrvk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Q07/wndeYYpkb1Dk/XG77IVlQ3CK9kED5WKR/R+C3O2wXHWkYB+8V226zEzEdZcwIuvW8/xhfXaRZO1RM31twfk20PTRjLps30IhuXuihxS8fuAR49/DCzDC324FxrBWdzo2ocJdo2kC4Uw5hVXGbPpisYMQ573hgDCo6MCXeaU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=114.94.151.114 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.61; Fri, 21 Nov 2025 18:59:42 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH v5 3/5] dt-bindings: clock: add Amlogic T7 peripherals clock controller Date: Fri, 21 Nov 2025 18:59:32 +0800 Message-ID: <20251121105934.1759745-4-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251121105934.1759745-1-jian.hu@amlogic.com> References: <20251121105934.1759745-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT bindings for the peripheral clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu Reviewed-by: Rob Herring (Arm) --- .../clock/amlogic,t7-peripherals-clkc.yaml | 116 +++++++++ .../clock/amlogic,t7-peripherals-clkc.h | 228 ++++++++++++++++++ 2 files changed, 344 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peri= pherals-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals= -clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals= -clkc.yaml new file mode 100644 index 000000000000..55bb73707d58 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.y= aml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T7 Peripherals Clock Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Xianwei Zhao + - Jian Hu + +properties: + compatible: + const: amlogic,t7-peripherals-clkc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 14 + items: + - description: input oscillator + - description: input sys clk + - description: input fixed pll + - description: input fclk div 2 + - description: input fclk div 2p5 + - description: input fclk div 3 + - description: input fclk div 4 + - description: input fclk div 5 + - description: input fclk div 7 + - description: input hifi pll + - description: input gp0 pll + - description: input gp1 pll + - description: input mpll1 + - description: input mpll2 + - description: external input rmii oscillator (optional) + - description: input video pll0 (optional) + - description: external pad input for rtc (optional) + + clock-names: + minItems: 14 + items: + - const: xtal + - const: sys + - const: fix + - const: fdiv2 + - const: fdiv2p5 + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: fdiv7 + - const: hifi + - const: gp0 + - const: gp1 + - const: mpll1 + - const: mpll2 + - const: ext_rmii + - const: vid_pll0 + - const: ext_rtc + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clkc_periphs:clock-controller@0 { + compatible =3D "amlogic,t7-peripherals-clkc"; + reg =3D <0 0x0 0 0x1c8>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk 13>, + <&scmi_clk 16>, + <&scmi_clk 18>, + <&scmi_clk 20>, + <&scmi_clk 22>, + <&scmi_clk 24>, + <&scmi_clk 26>, + <&scmi_clk 28>, + <&hifi 1>, + <&gp0 1>, + <&gp1 1>, + <&mpll 4>, + <&mpll 6>; + clock-names =3D "xtal", + "sys", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "hifi", + "gp0", + "gp1", + "mpll1", + "mpll2"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,t7-peripherals-clkc.h new file mode 100644 index 000000000000..e3bbfe517f1f --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved + */ + +#ifndef __T7_PERIPHERALS_CLKC_H +#define __T7_PERIPHERALS_CLKC_H + +#define CLKID_RTC_DUALDIV_IN 0 +#define CLKID_RTC_DUALDIV_DIV 1 +#define CLKID_RTC_DUALDIV_SEL 2 +#define CLKID_RTC_DUALDIV 3 +#define CLKID_RTC 4 +#define CLKID_CECA_DUALDIV_IN 5 +#define CLKID_CECA_DUALDIV_DIV 6 +#define CLKID_CECA_DUALDIV_SEL 7 +#define CLKID_CECA_DUALDIV 8 +#define CLKID_CECA 9 +#define CLKID_CECB_DUALDIV_IN 10 +#define CLKID_CECB_DUALDIV_DIV 11 +#define CLKID_CECB_DUALDIV_SEL 12 +#define CLKID_CECB_DUALDIV 13 +#define CLKID_CECB 14 +#define CLKID_SC_SEL 15 +#define CLKID_SC_DIV 16 +#define CLKID_SC 17 +#define CLKID_DSPA_0_SEL 18 +#define CLKID_DSPA_0_DIV 19 +#define CLKID_DSPA_0 20 +#define CLKID_DSPA_1_SEL 21 +#define CLKID_DSPA_1_DIV 22 +#define CLKID_DSPA_1 23 +#define CLKID_DSPA 24 +#define CLKID_DSPB_0_SEL 25 +#define CLKID_DSPB_0_DIV 26 +#define CLKID_DSPB_0 27 +#define CLKID_DSPB_1_SEL 28 +#define CLKID_DSPB_1_DIV 29 +#define CLKID_DSPB_1 30 +#define CLKID_DSPB 31 +#define CLKID_24M 32 +#define CLKID_24M_DIV2 33 +#define CLKID_12M 34 +#define CLKID_25M_DIV 35 +#define CLKID_25M 36 +#define CLKID_ANAKIN_0_SEL 37 +#define CLKID_ANAKIN_0_DIV 38 +#define CLKID_ANAKIN_0 39 +#define CLKID_ANAKIN_1_SEL 40 +#define CLKID_ANAKIN_1_DIV 41 +#define CLKID_ANAKIN_1 42 +#define CLKID_ANAKIN_01_SEL 43 +#define CLKID_ANAKIN 44 +#define CLKID_TS_DIV 45 +#define CLKID_TS 46 +#define CLKID_MIPI_CSI_PHY_0_SEL 47 +#define CLKID_MIPI_CSI_PHY_0_DIV 48 +#define CLKID_MIPI_CSI_PHY_0 49 +#define CLKID_MIPI_CSI_PHY_1_SEL 50 +#define CLKID_MIPI_CSI_PHY_1_DIV 51 +#define CLKID_MIPI_CSI_PHY_1 52 +#define CLKID_MIPI_CSI_PHY 53 +#define CLKID_MIPI_ISP_SEL 54 +#define CLKID_MIPI_ISP_DIV 55 +#define CLKID_MIPI_ISP 56 +#define CLKID_MALI_0_SEL 57 +#define CLKID_MALI_0_DIV 58 +#define CLKID_MALI_0 59 +#define CLKID_MALI_1_SEL 60 +#define CLKID_MALI_1_DIV 61 +#define CLKID_MALI_1 62 +#define CLKID_MALI 63 +#define CLKID_ETH_RMII_SEL 64 +#define CLKID_ETH_RMII_DIV 65 +#define CLKID_ETH_RMII 66 +#define CLKID_FCLK_DIV2_DIV8 67 +#define CLKID_ETH_125M 68 +#define CLKID_SD_EMMC_C_SEL 69 +#define CLKID_SD_EMMC_C_DIV 70 +#define CLKID_SD_EMMC_C 71 +#define CLKID_SD_EMMC_A_SEL 72 +#define CLKID_SD_EMMC_A_DIV 73 +#define CLKID_SD_EMMC_A 74 +#define CLKID_SD_EMMC_B_SEL 75 +#define CLKID_SD_EMMC_B_DIV 76 +#define CLKID_SD_EMMC_B 77 +#define CLKID_SPICC0_SEL 78 +#define CLKID_SPICC0_DIV 79 +#define CLKID_SPICC0 80 +#define CLKID_SPICC1_SEL 81 +#define CLKID_SPICC1_DIV 82 +#define CLKID_SPICC1 83 +#define CLKID_SPICC2_SEL 84 +#define CLKID_SPICC2_DIV 85 +#define CLKID_SPICC2 86 +#define CLKID_SPICC3_SEL 87 +#define CLKID_SPICC3_DIV 88 +#define CLKID_SPICC3 89 +#define CLKID_SPICC4_SEL 90 +#define CLKID_SPICC4_DIV 91 +#define CLKID_SPICC4 92 +#define CLKID_SPICC5_SEL 93 +#define CLKID_SPICC5_DIV 94 +#define CLKID_SPICC5 95 +#define CLKID_SARADC_SEL 96 +#define CLKID_SARADC_DIV 97 +#define CLKID_SARADC 98 +#define CLKID_PWM_A_SEL 99 +#define CLKID_PWM_A_DIV 100 +#define CLKID_PWM_A 101 +#define CLKID_PWM_B_SEL 102 +#define CLKID_PWM_B_DIV 103 +#define CLKID_PWM_B 104 +#define CLKID_PWM_C_SEL 105 +#define CLKID_PWM_C_DIV 106 +#define CLKID_PWM_C 107 +#define CLKID_PWM_D_SEL 108 +#define CLKID_PWM_D_DIV 109 +#define CLKID_PWM_D 110 +#define CLKID_PWM_E_SEL 111 +#define CLKID_PWM_E_DIV 112 +#define CLKID_PWM_E 113 +#define CLKID_PWM_F_SEL 114 +#define CLKID_PWM_F_DIV 115 +#define CLKID_PWM_F 116 +#define CLKID_PWM_AO_A_SEL 117 +#define CLKID_PWM_AO_A_DIV 118 +#define CLKID_PWM_AO_A 119 +#define CLKID_PWM_AO_B_SEL 120 +#define CLKID_PWM_AO_B_DIV 121 +#define CLKID_PWM_AO_B 122 +#define CLKID_PWM_AO_C_SEL 123 +#define CLKID_PWM_AO_C_DIV 124 +#define CLKID_PWM_AO_C 125 +#define CLKID_PWM_AO_D_SEL 126 +#define CLKID_PWM_AO_D_DIV 127 +#define CLKID_PWM_AO_D 128 +#define CLKID_PWM_AO_E_SEL 129 +#define CLKID_PWM_AO_E_DIV 130 +#define CLKID_PWM_AO_E 131 +#define CLKID_PWM_AO_F_SEL 132 +#define CLKID_PWM_AO_F_DIV 133 +#define CLKID_PWM_AO_F 134 +#define CLKID_PWM_AO_G_SEL 135 +#define CLKID_PWM_AO_G_DIV 136 +#define CLKID_PWM_AO_G 137 +#define CLKID_PWM_AO_H_SEL 138 +#define CLKID_PWM_AO_H_DIV 139 +#define CLKID_PWM_AO_H 140 +#define CLKID_SYS_DDR 141 +#define CLKID_SYS_DOS 142 +#define CLKID_SYS_MIPI_DSI_A 143 +#define CLKID_SYS_MIPI_DSI_B 144 +#define CLKID_SYS_ETHPHY 145 +#define CLKID_SYS_MALI 146 +#define CLKID_SYS_AOCPU 147 +#define CLKID_SYS_AUCPU 148 +#define CLKID_SYS_CEC 149 +#define CLKID_SYS_GDC 150 +#define CLKID_SYS_DESWARP 151 +#define CLKID_SYS_AMPIPE_NAND 152 +#define CLKID_SYS_AMPIPE_ETH 153 +#define CLKID_SYS_AM2AXI0 154 +#define CLKID_SYS_AM2AXI1 155 +#define CLKID_SYS_AM2AXI2 156 +#define CLKID_SYS_SD_EMMC_A 157 +#define CLKID_SYS_SD_EMMC_B 158 +#define CLKID_SYS_SD_EMMC_C 159 +#define CLKID_SYS_SMARTCARD 160 +#define CLKID_SYS_ACODEC 161 +#define CLKID_SYS_SPIFC 162 +#define CLKID_SYS_MSR_CLK 163 +#define CLKID_SYS_IR_CTRL 164 +#define CLKID_SYS_AUDIO 165 +#define CLKID_SYS_ETH 166 +#define CLKID_SYS_UART_A 167 +#define CLKID_SYS_UART_B 168 +#define CLKID_SYS_UART_C 169 +#define CLKID_SYS_UART_D 170 +#define CLKID_SYS_UART_E 171 +#define CLKID_SYS_UART_F 172 +#define CLKID_SYS_AIFIFO 173 +#define CLKID_SYS_SPICC2 174 +#define CLKID_SYS_SPICC3 175 +#define CLKID_SYS_SPICC4 176 +#define CLKID_SYS_TS_A73 177 +#define CLKID_SYS_TS_A53 178 +#define CLKID_SYS_SPICC5 179 +#define CLKID_SYS_G2D 180 +#define CLKID_SYS_SPICC0 181 +#define CLKID_SYS_SPICC1 182 +#define CLKID_SYS_PCIE 183 +#define CLKID_SYS_USB 184 +#define CLKID_SYS_PCIE_PHY 185 +#define CLKID_SYS_I2C_AO_A 186 +#define CLKID_SYS_I2C_AO_B 187 +#define CLKID_SYS_I2C_M_A 188 +#define CLKID_SYS_I2C_M_B 189 +#define CLKID_SYS_I2C_M_C 190 +#define CLKID_SYS_I2C_M_D 191 +#define CLKID_SYS_I2C_M_E 192 +#define CLKID_SYS_I2C_M_F 193 +#define CLKID_SYS_HDMITX_APB 194 +#define CLKID_SYS_I2C_S_A 195 +#define CLKID_SYS_HDMIRX_PCLK 196 +#define CLKID_SYS_MMC_APB 197 +#define CLKID_SYS_MIPI_ISP_PCLK 198 +#define CLKID_SYS_RSA 199 +#define CLKID_SYS_PCLK_SYS_APB 200 +#define CLKID_SYS_A73PCLK_APB 201 +#define CLKID_SYS_DSPA 202 +#define CLKID_SYS_DSPB 203 +#define CLKID_SYS_VPU_INTR 204 +#define CLKID_SYS_SAR_ADC 205 +#define CLKID_SYS_GIC 206 +#define CLKID_SYS_TS_GPU 207 +#define CLKID_SYS_TS_NNA 208 +#define CLKID_SYS_TS_VPU 209 +#define CLKID_SYS_TS_HEVC 210 +#define CLKID_SYS_PWM_AB 211 +#define CLKID_SYS_PWM_CD 212 +#define CLKID_SYS_PWM_EF 213 +#define CLKID_SYS_PWM_AO_AB 214 +#define CLKID_SYS_PWM_AO_CD 215 +#define CLKID_SYS_PWM_AO_EF 216 +#define CLKID_SYS_PWM_AO_GH 217 + +#endif /* __T7_PERIPHERALS_CLKC_H */ --=20 2.47.1 From nobody Tue Dec 2 01:28:36 2025 Received: from mail-sh.amlogic.com (unknown [114.94.151.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDF5C28750C; Fri, 21 Nov 2025 11:00:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.94.151.114 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Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.61; Fri, 21 Nov 2025 18:59:42 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH v5 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Date: Fri, 21 Nov 2025 18:59:33 +0800 Message-ID: <20251121105934.1759745-5-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251121105934.1759745-1-jian.hu@amlogic.com> References: <20251121105934.1759745-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PLL clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu --- drivers/clk/meson/Kconfig | 14 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/t7-pll.c | 1068 ++++++++++++++++++++++++++++++++++++ 3 files changed, 1083 insertions(+) create mode 100644 drivers/clk/meson/t7-pll.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 71481607a6d5..6cdc6a96e105 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -201,4 +201,18 @@ config COMMON_CLK_S4_PERIPHERALS help Support for the peripherals clock controller on Amlogic S805X2 and S905= Y4 devices, AKA S4. Say Y if you want S4 peripherals clock controller to w= ork. + +config COMMON_CLK_T7_PLL + tristate "Amlogic T7 SoC PLL controller support" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_PLL + imply COMMON_CLK_SCMI + help + Support for the PLL clock controller on Amlogic A311D2 based + device, AKA T7. PLLs are required by most peripheral to operate + Say Y if you are a T7 based device. + endmenu diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index c6998e752c68..8e3f7f94c639 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) +=3D g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o meson8-ddr.o obj-$(CONFIG_COMMON_CLK_S4_PLL) +=3D s4-pll.o obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) +=3D s4-peripherals.o +obj-$(CONFIG_COMMON_CLK_T7_PLL) +=3D t7-pll.o diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c new file mode 100644 index 000000000000..bee8a7489371 --- /dev/null +++ b/drivers/clk/meson/t7-pll.c @@ -0,0 +1,1068 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-mpll.h" +#include "meson-clkc-utils.h" +#include + +#define GP0PLL_CTRL0 0x00 +#define GP0PLL_CTRL1 0x04 +#define GP0PLL_CTRL2 0x08 +#define GP0PLL_CTRL3 0x0c +#define GP0PLL_CTRL4 0x10 +#define GP0PLL_CTRL5 0x14 +#define GP0PLL_CTRL6 0x18 +#define GP0PLL_STS 0x1c +#define GP1PLL_CTRL0 0x00 +#define GP1PLL_CTRL1 0x04 +#define GP1PLL_CTRL2 0x08 +#define GP1PLL_CTRL3 0x0c +#define GP1PLL_STS 0x1c +#define HIFIPLL_CTRL0 0x00 +#define HIFIPLL_CTRL1 0x04 +#define HIFIPLL_CTRL2 0x08 +#define HIFIPLL_CTRL3 0x0c +#define HIFIPLL_CTRL4 0x10 +#define HIFIPLL_CTRL5 0x14 +#define HIFIPLL_CTRL6 0x18 +#define HIFIPLL_STS 0x1c +#define PCIEPLL_CTRL0 0x00 +#define PCIEPLL_CTRL1 0x04 +#define PCIEPLL_CTRL2 0x08 +#define PCIEPLL_CTRL3 0x0c +#define PCIEPLL_CTRL4 0x10 +#define PCIEPLL_CTRL5 0x14 +#define PCIEPLL_STS 0x18 +#define MPLL_CTRL0 0x00 +#define MPLL_CTRL1 0x04 +#define MPLL_CTRL2 0x08 +#define MPLL_CTRL3 0x0c +#define MPLL_CTRL4 0x10 +#define MPLL_CTRL5 0x14 +#define MPLL_CTRL6 0x18 +#define MPLL_CTRL7 0x1c +#define MPLL_CTRL8 0x20 +#define MPLL_STS 0x24 +#define HDMIPLL_CTRL0 0x00 +#define HDMIPLL_CTRL1 0x04 +#define HDMIPLL_CTRL2 0x08 +#define HDMIPLL_CTRL3 0x0c +#define HDMIPLL_CTRL4 0x10 +#define HDMIPLL_CTRL5 0x14 +#define HDMIPLL_CTRL6 0x18 +#define HDMIPLL_STS 0x1c +#define MCLK_PLL_CNTL0 0x00 +#define MCLK_PLL_CNTL1 0x04 +#define MCLK_PLL_CNTL2 0x08 +#define MCLK_PLL_CNTL3 0x0c +#define MCLK_PLL_CNTL4 0x10 +#define MCLK_PLL_STS 0x14 + +static const struct pll_mult_range t7_media_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static const struct reg_sequence t7_gp0_init_regs[] =3D { + { .reg =3D GP0PLL_CTRL1, .def =3D 0x00000000 }, + { .reg =3D GP0PLL_CTRL2, .def =3D 0x00000000 }, + { .reg =3D GP0PLL_CTRL3, .def =3D 0x48681c00 }, + { .reg =3D GP0PLL_CTRL4, .def =3D 0x88770290 }, + { .reg =3D GP0PLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D GP0PLL_CTRL6, .def =3D 0x56540000 }, +}; + +static struct clk_regmap t7_gp0_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D GP0PLL_STS, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &t7_media_pll_mult_range, + .init_regs =3D t7_gp0_init_regs, + .init_count =3D ARRAY_SIZE(t7_gp0_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "gp0_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_gp0_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D GP0PLL_CTRL0, + .shift =3D 16, + .width =3D 3, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_gp0_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * The gp1 pll IP is different with gp0 pll, the PLL DCO range is + * 1.6GHZ - 3.2GHZ, and the reg_sequence is short + */ +static const struct pll_mult_range t7_gp1_pll_mult_range =3D { + .min =3D 67, + .max =3D 133, +}; + +static const struct reg_sequence t7_gp1_init_regs[] =3D { + { .reg =3D GP1PLL_CTRL1, .def =3D 0x1420500f }, + { .reg =3D GP1PLL_CTRL2, .def =3D 0x00023001 }, + { .reg =3D GP1PLL_CTRL3, .def =3D 0x00000000 }, +}; + +static struct clk_regmap t7_gp1_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D GP1PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D GP1PLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D GP1PLL_CTRL0, + .shift =3D 16, + .width =3D 5, + }, + .l =3D { + .reg_off =3D GP1PLL_STS, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D GP1PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &t7_gp1_pll_mult_range, + .init_regs =3D t7_gp1_init_regs, + .init_count =3D ARRAY_SIZE(t7_gp1_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "gp1_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_gp1_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D GP1PLL_CTRL0, + .shift =3D 12, + .width =3D 3, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp1_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_gp1_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_hifi_init_regs[] =3D { + { .reg =3D HIFIPLL_CTRL1, .def =3D 0x00000000 }, + { .reg =3D HIFIPLL_CTRL2, .def =3D 0x00000000 }, + { .reg =3D HIFIPLL_CTRL3, .def =3D 0x6a285c00 }, + { .reg =3D HIFIPLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D HIFIPLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D HIFIPLL_CTRL6, .def =3D 0x56540000 } +}; + +static struct clk_regmap t7_hifi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .frac =3D { + .reg_off =3D HIFIPLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .l =3D { + .reg_off =3D HIFIPLL_STS, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &t7_media_pll_mult_range, + .init_regs =3D t7_hifi_init_regs, + .init_count =3D ARRAY_SIZE(t7_hifi_init_regs), + .frac_max =3D 100000, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hifi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_hifi_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HIFIPLL_CTRL0, + .shift =3D 16, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_hifi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * The T7 PCIE PLL is fined tuned to deliver a very precise + * 100MHz reference clock for the PCIe Analog PHY, and thus requires + * a strict register sequence to enable the PLL. + */ +static const struct reg_sequence t7_pcie_pll_init_regs[] =3D { + { .reg =3D PCIEPLL_CTRL0, .def =3D 0x200c04c8 }, + { .reg =3D PCIEPLL_CTRL0, .def =3D 0x300c04c8 }, + { .reg =3D PCIEPLL_CTRL1, .def =3D 0x30000000 }, + { .reg =3D PCIEPLL_CTRL2, .def =3D 0x00001100 }, + { .reg =3D PCIEPLL_CTRL3, .def =3D 0x10058e00 }, + { .reg =3D PCIEPLL_CTRL4, .def =3D 0x000100c0 }, + { .reg =3D PCIEPLL_CTRL5, .def =3D 0x68000048 }, + { .reg =3D PCIEPLL_CTRL5, .def =3D 0x68000068, .delay_us =3D 20 }, + { .reg =3D PCIEPLL_CTRL4, .def =3D 0x008100c0, .delay_us =3D 20 }, + { .reg =3D PCIEPLL_CTRL0, .def =3D 0x340c04c8 }, + { .reg =3D PCIEPLL_CTRL0, .def =3D 0x140c04c8, .delay_us =3D 20 }, + { .reg =3D PCIEPLL_CTRL2, .def =3D 0x00001000 } +}; + +static struct clk_regmap t7_pcie_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D PCIEPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_pcie_pll_init_regs, + .init_count =3D ARRAY_SIZE(t7_pcie_pll_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pcie_pll_dco", + .ops =3D &meson_clk_pcie_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor t7_pcie_pll_dco_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pcie_pll_dco_div2", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_pcie_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_pcie_pll_od =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D PCIEPLL_CTRL0, + .shift =3D 16, + .width =3D 5, + /* the divisor is 32 when [16:21] =3D 0 */ + .flags =3D CLK_DIVIDER_MAX_AT_ZERO, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pcie_pll_od", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_pcie_pll_dco_div2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor t7_pcie_pll =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pcie_pll", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_pcie_pll_od.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor t7_mpll_prediv =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll_prediv", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +static const struct reg_sequence t7_mpll0_init_regs[] =3D { + { .reg =3D MPLL_CTRL2, .def =3D 0x40000033 } +}; + +static struct clk_regmap t7_mpll0_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_mpll0_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll0_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_mpll0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL1, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mpll0_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_mpll1_init_regs[] =3D { + { .reg =3D MPLL_CTRL4, .def =3D 0x40000033 } +}; + +static struct clk_regmap t7_mpll1_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_mpll1_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll1_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll1_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_mpll1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL3, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mpll1_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_mpll2_init_regs[] =3D { + { .reg =3D MPLL_CTRL6, .def =3D 0x40000033 } +}; + +static struct clk_regmap t7_mpll2_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_mpll2_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll2_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_mpll2 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL5, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mpll2_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_mpll3_init_regs[] =3D { + { .reg =3D MPLL_CTRL8, .def =3D 0x40000033 } +}; + +static struct clk_regmap t7_mpll3_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D t7_mpll3_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll3_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_mpll3 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL7, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mpll3_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_hdmi_init_regs[] =3D { + { .reg =3D HDMIPLL_CTRL1, .def =3D 0x00000000 }, + { .reg =3D HDMIPLL_CTRL2, .def =3D 0x00000000 }, + { .reg =3D HDMIPLL_CTRL3, .def =3D 0x6a28dc00 }, + { .reg =3D HDMIPLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D HDMIPLL_CTRL5, .def =3D 0x39272000 }, + { .reg =3D HDMIPLL_CTRL6, .def =3D 0x56540000 } +}; + +static struct clk_regmap t7_hdmi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 0, + .width =3D 9, + }, + .n =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HDMIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &t7_media_pll_mult_range, + .init_regs =3D t7_hdmi_init_regs, + .init_count =3D ARRAY_SIZE(t7_hdmi_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hdmi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "in0", } + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_hdmi_pll_od =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HDMIPLL_CTRL0, + .shift =3D 16, + .width =3D 4, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hdmi_pll_od", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_hdmi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_hdmi_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HDMIPLL_CTRL0, + .shift =3D 20, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hdmi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_hdmi_pll_od.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct pll_mult_range t7_mclk_pll_mult_range =3D { + .min =3D 67, + .max =3D 133, +}; + +static const struct reg_sequence t7_mclk_init_regs[] =3D { + { .reg =3D MCLK_PLL_CNTL1, .def =3D 0x1470500f }, + { .reg =3D MCLK_PLL_CNTL2, .def =3D 0x00023001 }, + { .reg =3D MCLK_PLL_CNTL3, .def =3D 0x18180000 }, + { .reg =3D MCLK_PLL_CNTL4, .def =3D 0x00180303 }, +}; + +static struct clk_regmap t7_mclk_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 16, + .width =3D 5, + }, + .l =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D MCLK_PLL_CNTL0, + .shift =3D 29, + .width =3D 1, + }, + .l_detect =3D { + .reg_off =3D MCLK_PLL_CNTL2, + .shift =3D 6, + .width =3D 1, + }, + .range =3D &t7_mclk_pll_mult_range, + .init_regs =3D t7_mclk_init_regs, + .init_count =3D ARRAY_SIZE(t7_mclk_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "in0", + }, + .num_parents =3D 1, + }, +}; + +/* max div is 16 */ +static const struct clk_div_table t7_mclk_div[] =3D { + { .val =3D 0, .div =3D 1 }, + { .val =3D 1, .div =3D 2 }, + { .val =3D 2, .div =3D 4 }, + { .val =3D 3, .div =3D 8 }, + { .val =3D 4, .div =3D 16 }, + { /* sentinel */ } +}; + +static struct clk_regmap t7_mclk_pre_od =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D MCLK_PLL_CNTL0, + .shift =3D 12, + .width =3D 3, + .table =3D t7_mclk_div, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_pre_od", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_pll =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D MCLK_PLL_CNTL4, + .shift =3D 16, + .width =3D 5, + .flags =3D CLK_DIVIDER_ONE_BASED, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_pre_od.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_0_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D MCLK_PLL_CNTL4, + .mask =3D 0x3, + .shift =3D 4, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .hw =3D &t7_mclk_pll.hw }, + { .fw_name =3D "in1", }, + { .fw_name =3D "in2", }, + }, + .num_parents =3D 3, + }, +}; + +static struct clk_fixed_factor t7_mclk_0_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_0_div2", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mclk_0_sel.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_0_pre =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MCLK_PLL_CNTL4, + .bit_idx =3D 2, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_0_pre", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_0_div2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MCLK_PLL_CNTL4, + .bit_idx =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_0_pre.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_1_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D MCLK_PLL_CNTL4, + .mask =3D 0x3, + .shift =3D 12, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .hw =3D &t7_mclk_pll.hw }, + { .fw_name =3D "in1", }, + { .fw_name =3D "in2", }, + }, + .num_parents =3D 3, + }, +}; + +static struct clk_fixed_factor t7_mclk_1_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mclk_1_div2", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_mclk_1_sel.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_1_pre =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MCLK_PLL_CNTL4, + .bit_idx =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_1_pre", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_1_div2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MCLK_PLL_CNTL4, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mclk_1_pre.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *t7_gp0_hw_clks[] =3D { + [CLKID_GP0_PLL_DCO] =3D &t7_gp0_pll_dco.hw, + [CLKID_GP0_PLL] =3D &t7_gp0_pll.hw, +}; + +static struct clk_hw *t7_gp1_hw_clks[] =3D { + [CLKID_GP1_PLL_DCO] =3D &t7_gp1_pll_dco.hw, + [CLKID_GP1_PLL] =3D &t7_gp1_pll.hw, +}; + +static struct clk_hw *t7_hifi_hw_clks[] =3D { + [CLKID_HIFI_PLL_DCO] =3D &t7_hifi_pll_dco.hw, + [CLKID_HIFI_PLL] =3D &t7_hifi_pll.hw, +}; + +static struct clk_hw *t7_pcie_hw_clks[] =3D { + [CLKID_PCIE_PLL_DCO] =3D &t7_pcie_pll_dco.hw, + [CLKID_PCIE_PLL_DCO_DIV2] =3D &t7_pcie_pll_dco_div2.hw, + [CLKID_PCIE_PLL_OD] =3D &t7_pcie_pll_od.hw, + [CLKID_PCIE_PLL] =3D &t7_pcie_pll.hw, +}; + +static struct clk_hw *t7_mpll_hw_clks[] =3D { + [CLKID_MPLL_PREDIV] =3D &t7_mpll_prediv.hw, + [CLKID_MPLL0_DIV] =3D &t7_mpll0_div.hw, + [CLKID_MPLL0] =3D &t7_mpll0.hw, + [CLKID_MPLL1_DIV] =3D &t7_mpll1_div.hw, + [CLKID_MPLL1] =3D &t7_mpll1.hw, + [CLKID_MPLL2_DIV] =3D &t7_mpll2_div.hw, + [CLKID_MPLL2] =3D &t7_mpll2.hw, + [CLKID_MPLL3_DIV] =3D &t7_mpll3_div.hw, + [CLKID_MPLL3] =3D &t7_mpll3.hw, +}; + +static struct clk_hw *t7_hdmi_hw_clks[] =3D { + [CLKID_HDMI_PLL_DCO] =3D &t7_hdmi_pll_dco.hw, + [CLKID_HDMI_PLL_OD] =3D &t7_hdmi_pll_od.hw, + [CLKID_HDMI_PLL] =3D &t7_hdmi_pll.hw, +}; + +static struct clk_hw *t7_mclk_hw_clks[] =3D { + [CLKID_MCLK_PLL_DCO] =3D &t7_mclk_pll_dco.hw, + [CLKID_MCLK_PRE] =3D &t7_mclk_pre_od.hw, + [CLKID_MCLK_PLL] =3D &t7_mclk_pll.hw, + [CLKID_MCLK_0_SEL] =3D &t7_mclk_0_sel.hw, + [CLKID_MCLK_0_DIV2] =3D &t7_mclk_0_div2.hw, + [CLKID_MCLK_0_PRE] =3D &t7_mclk_0_pre.hw, + [CLKID_MCLK_0] =3D &t7_mclk_0.hw, + [CLKID_MCLK_1_SEL] =3D &t7_mclk_1_sel.hw, + [CLKID_MCLK_1_DIV2] =3D &t7_mclk_1_div2.hw, + [CLKID_MCLK_1_PRE] =3D &t7_mclk_1_pre.hw, + [CLKID_MCLK_1] =3D &t7_mclk_1.hw, +}; + +static const struct meson_clkc_data t7_gp0_data =3D { + .hw_clks =3D { + .hws =3D t7_gp0_hw_clks, + .num =3D ARRAY_SIZE(t7_gp0_hw_clks), + }, +}; + +static const struct meson_clkc_data t7_gp1_data =3D { + .hw_clks =3D { + .hws =3D t7_gp1_hw_clks, + .num =3D ARRAY_SIZE(t7_gp1_hw_clks), + }, +}; + +static const struct meson_clkc_data t7_hifi_data =3D { + .hw_clks =3D { + .hws =3D t7_hifi_hw_clks, + .num =3D ARRAY_SIZE(t7_hifi_hw_clks), + }, +}; + +static const struct meson_clkc_data t7_pcie_data =3D { + .hw_clks =3D { + .hws =3D t7_pcie_hw_clks, + .num =3D ARRAY_SIZE(t7_pcie_hw_clks), + }, +}; + +static const struct reg_sequence t7_mpll_init_regs[] =3D { + { .reg =3D MPLL_CTRL0, .def =3D 0x00000543 } +}; + +static const struct meson_clkc_data t7_mpll_data =3D { + .hw_clks =3D { + .hws =3D t7_mpll_hw_clks, + .num =3D ARRAY_SIZE(t7_mpll_hw_clks), + }, + .init_regs =3D t7_mpll_init_regs, + .init_count =3D ARRAY_SIZE(t7_mpll_init_regs), +}; + +static const struct meson_clkc_data t7_hdmi_data =3D { + .hw_clks =3D { + .hws =3D t7_hdmi_hw_clks, + .num =3D ARRAY_SIZE(t7_hdmi_hw_clks), + }, +}; + +static const struct meson_clkc_data t7_mclk_data =3D { + .hw_clks =3D { + .hws =3D t7_mclk_hw_clks, + .num =3D ARRAY_SIZE(t7_mclk_hw_clks), + }, +}; + +static const struct of_device_id t7_pll_clkc_match_table[] =3D { + { .compatible =3D "amlogic,t7-gp0-pll", .data =3D &t7_gp0_data, }, + { .compatible =3D "amlogic,t7-gp1-pll", .data =3D &t7_gp1_data, }, + { .compatible =3D "amlogic,t7-hifi-pll", .data =3D &t7_hifi_data, }, + { .compatible =3D "amlogic,t7-pcie-pll", .data =3D &t7_pcie_data, }, + { .compatible =3D "amlogic,t7-mpll", .data =3D &t7_mpll_data, }, + { .compatible =3D "amlogic,t7-hdmi-pll", .data =3D &t7_hdmi_data, }, + { .compatible =3D "amlogic,t7-mclk-pll", .data =3D &t7_mclk_data, }, + {} +}; +MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table); + +static struct platform_driver t7_pll_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "t7-pll-clkc", + .of_match_table =3D t7_pll_clkc_match_table, + }, +}; +module_platform_driver(t7_pll_clkc_driver); + +MODULE_DESCRIPTION("Amlogic T7 PLL Clock Controller driver"); +MODULE_AUTHOR("Jian Hu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.47.1 From nobody Tue Dec 2 01:28:36 2025 Received: from mail-sh.amlogic.com (unknown [114.94.151.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C27AE346E51; Fri, 21 Nov 2025 11:01:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.94.151.114 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763722864; cv=none; b=ukOX0hW+hypEIbOfZipuKCh84p+ZcBCd/gkJlIJz2O7+m5DmLwurDNdEHTR84cWjQZrmPxu6Lm0DuegEGjEuS+Zc1zRQU1kUN2kCYhMqM/9wD45Q0FhIKlZj2ZsjZHclG3adrDnEpUC/u8D7sPX8T2khE6Qu+dMNbwzbFaN3sFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763722864; c=relaxed/simple; bh=5SRfzmQcnQHbHc7gwobC40fAgLT9/HGn1I3UYZgWLt4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pj5g9kxEU9NgcF6eWOhOY3PGSI+WOA4A5rNm3rKABJMnRI4caBzyLFrG5FM7aBQ0ZYzNrNrPhL3XM3p42z5b3I2Y9UvTDCtW6RA/CjoLV6Yaz7CUE5rQ953NEwRs4sA/6NkzpCoopsv0ayUuedZC7PH3VGsgmy8L1RfSI4mlIEM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=114.94.151.114 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.61; Fri, 21 Nov 2025 19:00:54 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH v5 5/5] clk: meson: t7: add t7 clock peripherals controller driver Date: Fri, 21 Nov 2025 18:59:34 +0800 Message-ID: <20251121105934.1759745-6-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251121105934.1759745-1-jian.hu@amlogic.com> References: <20251121105934.1759745-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Peripheral clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/t7-peripherals.c | 1266 ++++++++++++++++++++++++++++ 3 files changed, 1280 insertions(+) create mode 100644 drivers/clk/meson/t7-peripherals.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 6cdc6a96e105..d2442ae0f5be 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -215,4 +215,17 @@ config COMMON_CLK_T7_PLL device, AKA T7. PLLs are required by most peripheral to operate Say Y if you are a T7 based device. =20 +config COMMON_CLK_T7_PERIPHERALS + tristate "Amlogic T7 SoC peripherals clock controller support" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_DUALDIV + imply COMMON_CLK_SCMI + imply COMMON_CLK_T7_PLL + help + Support for the Peripherals clock controller on Amlogic A311D2 based + device, AKA T7. Peripherals are required by most peripheral to operate + Say Y if you are a T7 based device. endmenu diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 8e3f7f94c639..c6719694a242 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o meson8-dd= r.o obj-$(CONFIG_COMMON_CLK_S4_PLL) +=3D s4-pll.o obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) +=3D s4-peripherals.o obj-$(CONFIG_COMMON_CLK_T7_PLL) +=3D t7-pll.o +obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) +=3D t7-peripherals.o diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peri= pherals.c new file mode 100644 index 000000000000..10e77456b0d0 --- /dev/null +++ b/drivers/clk/meson/t7-peripherals.c @@ -0,0 +1,1266 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + */ + +#include +#include +#include "clk-dualdiv.h" +#include "clk-regmap.h" +#include "meson-clkc-utils.h" +#include + +#define RTC_BY_OSCIN_CTRL0 0x8 +#define RTC_BY_OSCIN_CTRL1 0xc +#define RTC_CTRL 0x10 +#define SYS_CLK_CTRL0 0x40 +#define SYS_CLK_EN0_REG0 0x44 +#define SYS_CLK_EN0_REG1 0x48 +#define SYS_CLK_EN0_REG2 0x4c +#define SYS_CLK_EN0_REG3 0x50 +#define CECA_CTRL0 0x88 +#define CECA_CTRL1 0x8c +#define CECB_CTRL0 0x90 +#define CECB_CTRL1 0x94 +#define SC_CLK_CTRL 0x98 +#define DSPA_CLK_CTRL0 0x9c +#define DSPB_CLK_CTRL0 0xa0 +#define CLK12_24_CTRL 0xa8 +#define ANAKIN_CLK_CTRL 0xac +#define MIPI_CSI_PHY_CLK_CTRL 0x10c +#define MIPI_ISP_CLK_CTRL 0x110 +#define TS_CLK_CTRL 0x158 +#define MALI_CLK_CTRL 0x15c +#define ETH_CLK_CTRL 0x164 +#define NAND_CLK_CTRL 0x168 +#define SD_EMMC_CLK_CTRL 0x16c +#define SPICC_CLK_CTRL 0x174 +#define SAR_CLK_CTRL0 0x17c +#define PWM_CLK_AB_CTRL 0x180 +#define PWM_CLK_CD_CTRL 0x184 +#define PWM_CLK_EF_CTRL 0x188 +#define PWM_CLK_AO_AB_CTRL 0x1a0 +#define PWM_CLK_AO_CD_CTRL 0x1a4 +#define PWM_CLK_AO_EF_CTRL 0x1a8 +#define PWM_CLK_AO_GH_CTRL 0x1ac +#define SPICC_CLK_CTRL1 0x1c0 +#define SPICC_CLK_CTRL2 0x1c4 + +#define T7_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(t7_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define T7_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(t7_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define T7_COMP_GATE(_name, _reg, _bit, _iflags) \ + MESON_COMP_GATE(t7_, _name, _reg, _bit, CLK_SET_RATE_PARENT | _iflags) + +static struct clk_regmap t7_rtc_dualdiv_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_duandiv_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static const struct meson_clk_dualdiv_param t7_dualdiv_table[] =3D { + { + .n1 =3D 733, .m1 =3D 8, + .n2 =3D 732, .m2 =3D 11, + .dual =3D 1, + }, + {} +}; + +static struct clk_regmap t7_rtc_dualdiv_div =3D { + .data =3D &(struct meson_clk_dualdiv_data){ + .n1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D t7_dualdiv_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "rtc_dualdiv_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_rtc_dualdiv_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_rtc_dualdiv_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_BY_OSCIN_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "rtc_dualdiv_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_rtc_dualdiv_div.hw, + &t7_rtc_dualdiv_in.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc_dualdiv =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_rtc_dualdiv_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_CTRL, + .mask =3D 0x3, + .shift =3D 0, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "rtc", + .ops =3D &clk_regmap_mux_ops, + /* The first and fourth clock sources are identical in RTC clock design.= */ + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &t7_rtc_dualdiv.hw }, + { .fw_name =3D "ext_rtc", }, + { .fw_name =3D "xtal", }, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_regmap t7_ceca_dualdiv_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CECA_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ceca_dualdiv_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_ceca_dualdiv_div =3D { + .data =3D &(struct meson_clk_dualdiv_data){ + .n1 =3D { + .reg_off =3D CECA_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D CECA_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D CECA_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D CECA_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D CECA_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D t7_dualdiv_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ceca_dualdiv_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ceca_dualdiv_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_ceca_dualdiv_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CECA_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ceca_dualdiv_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ceca_dualdiv_div.hw, + &t7_ceca_dualdiv_in.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ceca_dualdiv =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CECA_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ceca_dualdiv", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ceca_dualdiv_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ceca =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CECA_CTRL1, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ceca", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ceca_dualdiv.hw, + &t7_rtc.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_cecb_dualdiv_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CECB_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cecb_dualdiv_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_cecb_dualdiv_div =3D { + .data =3D &(struct meson_clk_dualdiv_data){ + .n1 =3D { + .reg_off =3D CECB_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D CECB_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D CECB_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D CECB_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D CECB_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D t7_dualdiv_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cecb_dualdiv_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_cecb_dualdiv_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_cecb_dualdiv_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CECB_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cecb_dualdiv_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_cecb_dualdiv_div.hw, + &t7_cecb_dualdiv_in.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_cecb_dualdiv =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CECB_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cecb_dualdiv", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_cecb_dualdiv_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_cecb =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CECB_CTRL1, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cecb", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_cecb_dualdiv.hw, + &t7_rtc.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data t7_sc_parents[] =3D { + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "xtal", }, +}; + +static T7_COMP_SEL(sc, SC_CLK_CTRL, 9, 0x3, t7_sc_parents); +static T7_COMP_DIV(sc, SC_CLK_CTRL, 0, 8); +static T7_COMP_GATE(sc, SC_CLK_CTRL, 8, 0); + +static const struct clk_parent_data t7_dsp_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "hifi", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv7", }, + { .hw =3D &t7_rtc.hw }, +}; + +static T7_COMP_SEL(dspa_0, DSPA_CLK_CTRL0, 10, 0x7, t7_dsp_parents); +static T7_COMP_DIV(dspa_0, DSPA_CLK_CTRL0, 0, 10); +static T7_COMP_GATE(dspa_0, DSPA_CLK_CTRL0, 13, CLK_SET_RATE_GATE); + +static T7_COMP_SEL(dspa_1, DSPA_CLK_CTRL0, 26, 0x7, t7_dsp_parents); +static T7_COMP_DIV(dspa_1, DSPA_CLK_CTRL0, 16, 10); +static T7_COMP_GATE(dspa_1, DSPA_CLK_CTRL0, 29, CLK_SET_RATE_GATE); + +static struct clk_regmap t7_dspa =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspa", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspa_0.hw, + &t7_dspa_1.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static T7_COMP_SEL(dspb_0, DSPB_CLK_CTRL0, 10, 0x7, t7_dsp_parents); +static T7_COMP_DIV(dspb_0, DSPB_CLK_CTRL0, 0, 10); +static T7_COMP_GATE(dspb_0, DSPB_CLK_CTRL0, 13, CLK_SET_RATE_GATE); + +static T7_COMP_SEL(dspb_1, DSPB_CLK_CTRL0, 26, 0x7, t7_dsp_parents); +static T7_COMP_DIV(dspb_1, DSPB_CLK_CTRL0, 16, 10); +static T7_COMP_GATE(dspb_1, DSPB_CLK_CTRL0, 29, CLK_SET_RATE_GATE); + +static struct clk_regmap t7_dspb =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPB_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspb", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspb_0.hw, + &t7_dspb_1.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_24m =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "24m", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor t7_24m_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "24m_div2", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_24m.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_12m =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "12m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_24m_div2.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_25m_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLK12_24_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "25m_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_25m =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 12, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "25m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_25m_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data t7_anakin_parents[] =3D { + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "vid_pll0", }, + { .fw_name =3D "mpll1", }, + { .fw_name =3D "mpll2", }, + { .fw_name =3D "fdiv2p5", }, +}; + +static T7_COMP_SEL(anakin_0, ANAKIN_CLK_CTRL, 9, 0x7, t7_anakin_parents); +static T7_COMP_DIV(anakin_0, ANAKIN_CLK_CTRL, 0, 7); +static T7_COMP_GATE(anakin_0, ANAKIN_CLK_CTRL, 8, CLK_SET_RATE_GATE); + +static T7_COMP_SEL(anakin_1, ANAKIN_CLK_CTRL, 25, 0x7, t7_anakin_parents); +static T7_COMP_DIV(anakin_1, ANAKIN_CLK_CTRL, 16, 7); +static T7_COMP_GATE(anakin_1, ANAKIN_CLK_CTRL, 24, CLK_SET_RATE_GATE); + +static struct clk_regmap t7_anakin_01_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D ANAKIN_CLK_CTRL, + .mask =3D 1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "anakin_01_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_anakin_0.hw, + &t7_anakin_1.hw + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT + }, +}; + +static struct clk_regmap t7_anakin =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D ANAKIN_CLK_CTRL, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "anakin", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_anakin_01_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT + }, +}; + +static const struct clk_parent_data t7_mipi_csi_phy_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "gp1", }, + { .fw_name =3D "mpll1", }, + { .fw_name =3D "mpll2", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, +}; + +static T7_COMP_SEL(mipi_csi_phy_0, MIPI_CSI_PHY_CLK_CTRL, 9, 0x7, t7_mipi_= csi_phy_parents); +static T7_COMP_DIV(mipi_csi_phy_0, MIPI_CSI_PHY_CLK_CTRL, 0, 7); +static T7_COMP_GATE(mipi_csi_phy_0, MIPI_CSI_PHY_CLK_CTRL, 8, CLK_SET_RATE= _GATE); + +static T7_COMP_SEL(mipi_csi_phy_1, MIPI_CSI_PHY_CLK_CTRL, 25, 0x7, t7_mipi= _csi_phy_parents); +static T7_COMP_DIV(mipi_csi_phy_1, MIPI_CSI_PHY_CLK_CTRL, 16, 7); +static T7_COMP_GATE(mipi_csi_phy_1, MIPI_CSI_PHY_CLK_CTRL, 24, CLK_SET_RAT= E_GATE); + +static struct clk_regmap t7_mipi_csi_phy =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D MIPI_CSI_PHY_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mipi_csi_phy", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mipi_csi_phy_0.hw, + &t7_mipi_csi_phy_1.hw + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data t7_mipi_isp_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "mpll2", }, + { .fw_name =3D "mpll3", }, + { .fw_name =3D "gp1", }, +}; + +static T7_COMP_SEL(mipi_isp, MIPI_ISP_CLK_CTRL, 9, 0x7, t7_mipi_isp_parent= s); +static T7_COMP_DIV(mipi_isp, MIPI_ISP_CLK_CTRL, 0, 7); +static T7_COMP_GATE(mipi_isp, MIPI_ISP_CLK_CTRL, 8, 0); + +static struct clk_regmap t7_ts_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ts_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_ts =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ts", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ts_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data t7_mali_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "gp1", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, +}; + +static T7_COMP_SEL(mali_0, MALI_CLK_CTRL, 9, 0x7, t7_mali_parents); +static T7_COMP_DIV(mali_0, MALI_CLK_CTRL, 0, 7); +static T7_COMP_GATE(mali_0, MALI_CLK_CTRL, 8, CLK_SET_RATE_GATE); + +static T7_COMP_SEL(mali_1, MALI_CLK_CTRL, 25, 0x7, t7_mali_parents); +static T7_COMP_DIV(mali_1, MALI_CLK_CTRL, 16, 7); +static T7_COMP_GATE(mali_1, MALI_CLK_CTRL, 24, CLK_SET_RATE_GATE); + +static struct clk_regmap t7_mali =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D MALI_CLK_CTRL, + .mask =3D 1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mali", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mali_0.hw, + &t7_mali_1.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * parent index 2, 3, 4, 5, 6 not connect any clock signal, + * the last parent connect external PAD + */ +static u32 t7_eth_rmii_parents_val_table[] =3D { 0, 1, 7 }; +static const struct clk_parent_data t7_eth_rmii_parents[] =3D { + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "gp1", }, + { .fw_name =3D "ext_rmii", }, +}; + +static struct clk_regmap t7_eth_rmii_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D ETH_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + .table =3D t7_eth_rmii_parents_val_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "eth_rmii_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_eth_rmii_parents, + .num_parents =3D ARRAY_SIZE(t7_eth_rmii_parents), + .flags =3D CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_regmap t7_eth_rmii_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ETH_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "eth_rmii_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_eth_rmii_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_eth_rmii =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "eth_rmii", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_eth_rmii_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor t7_fdiv2_div8 =3D { + .mult =3D 1, + .div =3D 8, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fdiv2_div8", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_eth_125m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "eth_125m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_fdiv2_div8.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_parent_data t7_sd_emmc_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "hifi", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "mpll2", }, + { .fw_name =3D "mpll3", }, + { .fw_name =3D "gp0", }, +}; + +static T7_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents); +static T7_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7); +static T7_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7, 0); + +static T7_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents= ); +static T7_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7); +static T7_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7, 0); + +static T7_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, t7_sd_emmc_parent= s); +static T7_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7); +static T7_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23, 0); + +static const struct clk_parent_data t7_spicc_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "sys", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "gp1", }, +}; + +static T7_COMP_SEL(spicc0, SPICC_CLK_CTRL, 7, 0x7, t7_spicc_parents); +static T7_COMP_DIV(spicc0, SPICC_CLK_CTRL, 0, 6); +static T7_COMP_GATE(spicc0, SPICC_CLK_CTRL, 6, 0); + +static T7_COMP_SEL(spicc1, SPICC_CLK_CTRL, 23, 0x7, t7_spicc_parents); +static T7_COMP_DIV(spicc1, SPICC_CLK_CTRL, 16, 6); +static T7_COMP_GATE(spicc1, SPICC_CLK_CTRL, 22, 0); + +static T7_COMP_SEL(spicc2, SPICC_CLK_CTRL1, 7, 0x7, t7_spicc_parents); +static T7_COMP_DIV(spicc2, SPICC_CLK_CTRL1, 0, 6); +static T7_COMP_GATE(spicc2, SPICC_CLK_CTRL1, 6, 0); + +static T7_COMP_SEL(spicc3, SPICC_CLK_CTRL1, 23, 0x7, t7_spicc_parents); +static T7_COMP_DIV(spicc3, SPICC_CLK_CTRL1, 16, 6); +static T7_COMP_GATE(spicc3, SPICC_CLK_CTRL1, 22, 0); + +static T7_COMP_SEL(spicc4, SPICC_CLK_CTRL2, 7, 0x7, t7_spicc_parents); +static T7_COMP_DIV(spicc4, SPICC_CLK_CTRL2, 0, 6); +static T7_COMP_GATE(spicc4, SPICC_CLK_CTRL2, 6, 0); + +static T7_COMP_SEL(spicc5, SPICC_CLK_CTRL2, 23, 0x7, t7_spicc_parents); +static T7_COMP_DIV(spicc5, SPICC_CLK_CTRL2, 16, 6); +static T7_COMP_GATE(spicc5, SPICC_CLK_CTRL2, 22, 0); + +static const struct clk_parent_data t7_saradc_parents[] =3D { + { .fw_name =3D "xtal" }, + { .fw_name =3D "sys" }, +}; + +static T7_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, t7_saradc_parents); +static T7_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8); +static T7_COMP_GATE(saradc, SAR_CLK_CTRL0, 8, 0); + +static const struct clk_parent_data t7_pwm_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "vid_pll0", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, +}; + +static T7_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); +static T7_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8, 0); + +static T7_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); +static T7_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24, 0); + +static T7_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); +static T7_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8, 0); + +static T7_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); +static T7_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24, 0); + +static T7_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); +static T7_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8, 0); + +static T7_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); +static T7_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24, 0); + +static T7_COMP_SEL(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 9, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 0, 8); +static T7_COMP_GATE(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 8, 0); + +static T7_COMP_SEL(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 25, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 16, 8); +static T7_COMP_GATE(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 24, 0); + +static T7_COMP_SEL(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 9, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 0, 8); +static T7_COMP_GATE(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 8, 0); + +static T7_COMP_SEL(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 25, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 16, 8); +static T7_COMP_GATE(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 24, 0); + +static T7_COMP_SEL(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 9, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 0, 8); +static T7_COMP_GATE(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 8, 0); + +static T7_COMP_SEL(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 25, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 16, 8); +static T7_COMP_GATE(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 24, 0); + +static T7_COMP_SEL(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 9, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 0, 8); +static T7_COMP_GATE(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 8, 0); + +static T7_COMP_SEL(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 25, 0x3, t7_pwm_parents); +static T7_COMP_DIV(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 16, 8); +static T7_COMP_GATE(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 24, 0); + +static const struct clk_parent_data t7_sys_pclk_parents =3D { .fw_name =3D= "sys" }; + +#define T7_SYS_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(t7_##_name, _reg, _bit, &t7_sys_pclk_parents, _flags) + +static T7_SYS_PCLK(sys_ddr, SYS_CLK_EN0_REG0, 0, 0); +static T7_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG0, 1, 0); +static T7_SYS_PCLK(sys_mipi_dsi_a, SYS_CLK_EN0_REG0, 2, 0); +static T7_SYS_PCLK(sys_mipi_dsi_b, SYS_CLK_EN0_REG0, 3, 0); +static T7_SYS_PCLK(sys_ethphy, SYS_CLK_EN0_REG0, 4, 0); +static T7_SYS_PCLK(sys_mali, SYS_CLK_EN0_REG0, 6, 0); +static T7_SYS_PCLK(sys_aocpu, SYS_CLK_EN0_REG0, 13, 0); +static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, 0); +static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0); +static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0); +static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0); +static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0); +static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); +static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, 0); +static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, 0); +static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, 0); +static T7_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG0, 24, 0); +static T7_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG0, 25, 0); +static T7_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG0, 26, 0); +static T7_SYS_PCLK(sys_smartcard, SYS_CLK_EN0_REG0, 27, 0); +static T7_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG0, 28, 0); +static T7_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 29, 0); +static T7_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 30, 0); +static T7_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 31, 0); +static T7_SYS_PCLK(sys_audio, SYS_CLK_EN0_REG1, 0, 0); +static T7_SYS_PCLK(sys_eth, SYS_CLK_EN0_REG1, 3, 0); +static T7_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 5, 0); +static T7_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 6, 0); +static T7_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 7, 0); +static T7_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 8, 0); +static T7_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 9, 0); +static T7_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG1, 10, 0); +static T7_SYS_PCLK(sys_aififo, SYS_CLK_EN0_REG1, 11, 0); +static T7_SYS_PCLK(sys_spicc2, SYS_CLK_EN0_REG1, 12, 0); +static T7_SYS_PCLK(sys_spicc3, SYS_CLK_EN0_REG1, 13, 0); +static T7_SYS_PCLK(sys_spicc4, SYS_CLK_EN0_REG1, 14, 0); +static T7_SYS_PCLK(sys_ts_a73, SYS_CLK_EN0_REG1, 15, 0); +static T7_SYS_PCLK(sys_ts_a53, SYS_CLK_EN0_REG1, 16, 0); +static T7_SYS_PCLK(sys_spicc5, SYS_CLK_EN0_REG1, 17, 0); +static T7_SYS_PCLK(sys_g2d, SYS_CLK_EN0_REG1, 20, 0); +static T7_SYS_PCLK(sys_spicc0, SYS_CLK_EN0_REG1, 21, 0); +static T7_SYS_PCLK(sys_spicc1, SYS_CLK_EN0_REG1, 22, 0); +static T7_SYS_PCLK(sys_pcie, SYS_CLK_EN0_REG1, 24, 0); +static T7_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 26, 0); +static T7_SYS_PCLK(sys_pcie_phy, SYS_CLK_EN0_REG1, 27, 0); +static T7_SYS_PCLK(sys_i2c_ao_a, SYS_CLK_EN0_REG1, 28, 0); +static T7_SYS_PCLK(sys_i2c_ao_b, SYS_CLK_EN0_REG1, 29, 0); +static T7_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 30, 0); +static T7_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 31, 0); +static T7_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG2, 0, 0); +static T7_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG2, 1, 0); +static T7_SYS_PCLK(sys_i2c_m_e, SYS_CLK_EN0_REG2, 2, 0); +static T7_SYS_PCLK(sys_i2c_m_f, SYS_CLK_EN0_REG2, 3, 0); +static T7_SYS_PCLK(sys_hdmitx_apb, SYS_CLK_EN0_REG2, 4, 0); +static T7_SYS_PCLK(sys_i2c_s_a, SYS_CLK_EN0_REG2, 5, 0); +static T7_SYS_PCLK(sys_hdmirx_pclk, SYS_CLK_EN0_REG2, 8, 0); +static T7_SYS_PCLK(sys_mmc_apb, SYS_CLK_EN0_REG2, 11, 0); +static T7_SYS_PCLK(sys_mipi_isp_pclk, SYS_CLK_EN0_REG2, 17, 0); +static T7_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG2, 18, 0); +static T7_SYS_PCLK(sys_pclk_sys_apb, SYS_CLK_EN0_REG2, 19, 0); +static T7_SYS_PCLK(sys_a73pclk_apb, SYS_CLK_EN0_REG2, 20, 0); +static T7_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG2, 21, 0); +static T7_SYS_PCLK(sys_dspb, SYS_CLK_EN0_REG2, 22, 0); +static T7_SYS_PCLK(sys_vpu_intr, SYS_CLK_EN0_REG2, 25, 0); +static T7_SYS_PCLK(sys_sar_adc, SYS_CLK_EN0_REG2, 28, 0); +/* + * sys_gic provides the clock for GIC(Generic Interrupt Controller). + * After clock is disabled, The GIC cannot work properly. At present, the = driver + * used by our GIC is the public driver in kernel, and there is no managem= ent + * clock in the driver. + */ +static T7_SYS_PCLK(sys_gic, SYS_CLK_EN0_REG2, 30, CLK_IS_CRITICAL); +static T7_SYS_PCLK(sys_ts_gpu, SYS_CLK_EN0_REG2, 31, 0); +static T7_SYS_PCLK(sys_ts_nna, SYS_CLK_EN0_REG3, 0, 0); +static T7_SYS_PCLK(sys_ts_vpu, SYS_CLK_EN0_REG3, 1, 0); +static T7_SYS_PCLK(sys_ts_hevc, SYS_CLK_EN0_REG3, 2, 0); +static T7_SYS_PCLK(sys_pwm_ao_ab, SYS_CLK_EN0_REG3, 3, 0); +static T7_SYS_PCLK(sys_pwm_ao_cd, SYS_CLK_EN0_REG3, 4, 0); +static T7_SYS_PCLK(sys_pwm_ao_ef, SYS_CLK_EN0_REG3, 5, 0); +static T7_SYS_PCLK(sys_pwm_ao_gh, SYS_CLK_EN0_REG3, 6, 0); +static T7_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG3, 7, 0); +static T7_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG3, 8, 0); +static T7_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG3, 9, 0); + +/* Array of all clocks registered by this provider */ +static struct clk_hw *t7_peripherals_hw_clks[] =3D { + [CLKID_RTC_DUALDIV_IN] =3D &t7_rtc_dualdiv_in.hw, + [CLKID_RTC_DUALDIV_DIV] =3D &t7_rtc_dualdiv_div.hw, + [CLKID_RTC_DUALDIV_SEL] =3D &t7_rtc_dualdiv_sel.hw, + [CLKID_RTC_DUALDIV] =3D &t7_rtc_dualdiv.hw, + [CLKID_RTC] =3D &t7_rtc.hw, + [CLKID_CECA_DUALDIV_IN] =3D &t7_ceca_dualdiv_in.hw, + [CLKID_CECA_DUALDIV_DIV] =3D &t7_ceca_dualdiv_div.hw, + [CLKID_CECA_DUALDIV_SEL] =3D &t7_ceca_dualdiv_sel.hw, + [CLKID_CECA_DUALDIV] =3D &t7_ceca_dualdiv.hw, + [CLKID_CECA] =3D &t7_ceca.hw, + [CLKID_CECB_DUALDIV_IN] =3D &t7_cecb_dualdiv_in.hw, + [CLKID_CECB_DUALDIV_DIV] =3D &t7_cecb_dualdiv_div.hw, + [CLKID_CECB_DUALDIV_SEL] =3D &t7_cecb_dualdiv_sel.hw, + [CLKID_CECB_DUALDIV] =3D &t7_cecb_dualdiv.hw, + [CLKID_CECB] =3D &t7_cecb.hw, + [CLKID_SC_SEL] =3D &t7_sc_sel.hw, + [CLKID_SC_DIV] =3D &t7_sc_div.hw, + [CLKID_SC] =3D &t7_sc.hw, + [CLKID_DSPA_0_SEL] =3D &t7_dspa_0_sel.hw, + [CLKID_DSPA_0_DIV] =3D &t7_dspa_0_div.hw, + [CLKID_DSPA_0] =3D &t7_dspa_0.hw, + [CLKID_DSPA_1_SEL] =3D &t7_dspa_1_sel.hw, + [CLKID_DSPA_1_DIV] =3D &t7_dspa_1_div.hw, + [CLKID_DSPA_1] =3D &t7_dspa_1.hw, + [CLKID_DSPA] =3D &t7_dspa.hw, + [CLKID_DSPB_0_SEL] =3D &t7_dspb_0_sel.hw, + [CLKID_DSPB_0_DIV] =3D &t7_dspb_0_div.hw, + [CLKID_DSPB_0] =3D &t7_dspb_0.hw, + [CLKID_DSPB_1_SEL] =3D &t7_dspb_1_sel.hw, + [CLKID_DSPB_1_DIV] =3D &t7_dspb_1_div.hw, + [CLKID_DSPB_1] =3D &t7_dspb_1.hw, + [CLKID_DSPB] =3D &t7_dspb.hw, + [CLKID_24M] =3D &t7_24m.hw, + [CLKID_24M_DIV2] =3D &t7_24m_div2.hw, + [CLKID_12M] =3D &t7_12m.hw, + [CLKID_25M_DIV] =3D &t7_25m_div.hw, + [CLKID_25M] =3D &t7_25m.hw, + [CLKID_ANAKIN_0_SEL] =3D &t7_anakin_0_sel.hw, + [CLKID_ANAKIN_0_DIV] =3D &t7_anakin_0_div.hw, + [CLKID_ANAKIN_0] =3D &t7_anakin_0.hw, + [CLKID_ANAKIN_1_SEL] =3D &t7_anakin_1_sel.hw, + [CLKID_ANAKIN_1_DIV] =3D &t7_anakin_1_div.hw, + [CLKID_ANAKIN_1] =3D &t7_anakin_1.hw, + [CLKID_ANAKIN_01_SEL] =3D &t7_anakin_01_sel.hw, + [CLKID_ANAKIN] =3D &t7_anakin.hw, + [CLKID_MIPI_CSI_PHY_0_SEL] =3D &t7_mipi_csi_phy_0_sel.hw, + [CLKID_MIPI_CSI_PHY_0_DIV] =3D &t7_mipi_csi_phy_0_div.hw, + [CLKID_MIPI_CSI_PHY_0] =3D &t7_mipi_csi_phy_0.hw, + [CLKID_MIPI_CSI_PHY_1_SEL] =3D &t7_mipi_csi_phy_1_sel.hw, + [CLKID_MIPI_CSI_PHY_1_DIV] =3D &t7_mipi_csi_phy_1_div.hw, + [CLKID_MIPI_CSI_PHY_1] =3D &t7_mipi_csi_phy_1.hw, + [CLKID_MIPI_CSI_PHY] =3D &t7_mipi_csi_phy.hw, + [CLKID_MIPI_ISP_SEL] =3D &t7_mipi_isp_sel.hw, + [CLKID_MIPI_ISP_DIV] =3D &t7_mipi_isp_div.hw, + [CLKID_MIPI_ISP] =3D &t7_mipi_isp.hw, + [CLKID_TS_DIV] =3D &t7_ts_div.hw, + [CLKID_TS] =3D &t7_ts.hw, + [CLKID_MALI_0_SEL] =3D &t7_mali_0_sel.hw, + [CLKID_MALI_0_DIV] =3D &t7_mali_0_div.hw, + [CLKID_MALI_0] =3D &t7_mali_0.hw, + [CLKID_MALI_1_SEL] =3D &t7_mali_1_sel.hw, + [CLKID_MALI_1_DIV] =3D &t7_mali_1_div.hw, + [CLKID_MALI_1] =3D &t7_mali_1.hw, + [CLKID_MALI] =3D &t7_mali.hw, + [CLKID_ETH_RMII_SEL] =3D &t7_eth_rmii_sel.hw, + [CLKID_ETH_RMII_DIV] =3D &t7_eth_rmii_div.hw, + [CLKID_ETH_RMII] =3D &t7_eth_rmii.hw, + [CLKID_FCLK_DIV2_DIV8] =3D &t7_fdiv2_div8.hw, + [CLKID_ETH_125M] =3D &t7_eth_125m.hw, + [CLKID_SD_EMMC_C_SEL] =3D &t7_sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &t7_sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &t7_sd_emmc_c.hw, + [CLKID_SD_EMMC_A_SEL] =3D &t7_sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &t7_sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &t7_sd_emmc_a.hw, + [CLKID_SD_EMMC_B_SEL] =3D &t7_sd_emmc_b_sel.hw, + [CLKID_SD_EMMC_B_DIV] =3D &t7_sd_emmc_b_div.hw, + [CLKID_SD_EMMC_B] =3D &t7_sd_emmc_b.hw, + [CLKID_SPICC0_SEL] =3D &t7_spicc0_sel.hw, + [CLKID_SPICC0_DIV] =3D &t7_spicc0_div.hw, + [CLKID_SPICC0] =3D &t7_spicc0.hw, + [CLKID_SPICC1_SEL] =3D &t7_spicc1_sel.hw, + [CLKID_SPICC1_DIV] =3D &t7_spicc1_div.hw, + [CLKID_SPICC1] =3D &t7_spicc1.hw, + [CLKID_SPICC2_SEL] =3D &t7_spicc2_sel.hw, + [CLKID_SPICC2_DIV] =3D &t7_spicc2_div.hw, + [CLKID_SPICC2] =3D &t7_spicc2.hw, + [CLKID_SPICC3_SEL] =3D &t7_spicc3_sel.hw, + [CLKID_SPICC3_DIV] =3D &t7_spicc3_div.hw, + [CLKID_SPICC3] =3D &t7_spicc3.hw, + [CLKID_SPICC4_SEL] =3D &t7_spicc4_sel.hw, + [CLKID_SPICC4_DIV] =3D &t7_spicc4_div.hw, + [CLKID_SPICC4] =3D &t7_spicc4.hw, + [CLKID_SPICC5_SEL] =3D &t7_spicc5_sel.hw, + [CLKID_SPICC5_DIV] =3D &t7_spicc5_div.hw, + [CLKID_SPICC5] =3D &t7_spicc5.hw, + [CLKID_SARADC_SEL] =3D &t7_saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &t7_saradc_div.hw, + [CLKID_SARADC] =3D &t7_saradc.hw, + [CLKID_PWM_A_SEL] =3D &t7_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &t7_pwm_a_div.hw, + [CLKID_PWM_A] =3D &t7_pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &t7_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &t7_pwm_b_div.hw, + [CLKID_PWM_B] =3D &t7_pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &t7_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &t7_pwm_c_div.hw, + [CLKID_PWM_C] =3D &t7_pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &t7_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &t7_pwm_d_div.hw, + [CLKID_PWM_D] =3D &t7_pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &t7_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &t7_pwm_e_div.hw, + [CLKID_PWM_E] =3D &t7_pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &t7_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &t7_pwm_f_div.hw, + [CLKID_PWM_F] =3D &t7_pwm_f.hw, + [CLKID_PWM_AO_A_SEL] =3D &t7_pwm_ao_a_sel.hw, + [CLKID_PWM_AO_A_DIV] =3D &t7_pwm_ao_a_div.hw, + [CLKID_PWM_AO_A] =3D &t7_pwm_ao_a.hw, + [CLKID_PWM_AO_B_SEL] =3D &t7_pwm_ao_b_sel.hw, + [CLKID_PWM_AO_B_DIV] =3D &t7_pwm_ao_b_div.hw, + [CLKID_PWM_AO_B] =3D &t7_pwm_ao_b.hw, + [CLKID_PWM_AO_C_SEL] =3D &t7_pwm_ao_c_sel.hw, + [CLKID_PWM_AO_C_DIV] =3D &t7_pwm_ao_c_div.hw, + [CLKID_PWM_AO_C] =3D &t7_pwm_ao_c.hw, + [CLKID_PWM_AO_D_SEL] =3D &t7_pwm_ao_d_sel.hw, + [CLKID_PWM_AO_D_DIV] =3D &t7_pwm_ao_d_div.hw, + [CLKID_PWM_AO_D] =3D &t7_pwm_ao_d.hw, + [CLKID_PWM_AO_E_SEL] =3D &t7_pwm_ao_e_sel.hw, + [CLKID_PWM_AO_E_DIV] =3D &t7_pwm_ao_e_div.hw, + [CLKID_PWM_AO_E] =3D &t7_pwm_ao_e.hw, + [CLKID_PWM_AO_F_SEL] =3D &t7_pwm_ao_f_sel.hw, + [CLKID_PWM_AO_F_DIV] =3D &t7_pwm_ao_f_div.hw, + [CLKID_PWM_AO_F] =3D &t7_pwm_ao_f.hw, + [CLKID_PWM_AO_G_SEL] =3D &t7_pwm_ao_g_sel.hw, + [CLKID_PWM_AO_G_DIV] =3D &t7_pwm_ao_g_div.hw, + [CLKID_PWM_AO_G] =3D &t7_pwm_ao_g.hw, + [CLKID_PWM_AO_H_SEL] =3D &t7_pwm_ao_h_sel.hw, + [CLKID_PWM_AO_H_DIV] =3D &t7_pwm_ao_h_div.hw, + [CLKID_PWM_AO_H] =3D &t7_pwm_ao_h.hw, + [CLKID_SYS_DDR] =3D &t7_sys_ddr.hw, + [CLKID_SYS_DOS] =3D &t7_sys_dos.hw, + [CLKID_SYS_MIPI_DSI_A] =3D &t7_sys_mipi_dsi_a.hw, + [CLKID_SYS_MIPI_DSI_B] =3D &t7_sys_mipi_dsi_b.hw, + [CLKID_SYS_ETHPHY] =3D &t7_sys_ethphy.hw, + [CLKID_SYS_MALI] =3D &t7_sys_mali.hw, + [CLKID_SYS_AOCPU] =3D &t7_sys_aocpu.hw, + [CLKID_SYS_AUCPU] =3D &t7_sys_aucpu.hw, + [CLKID_SYS_CEC] =3D &t7_sys_cec.hw, + [CLKID_SYS_GDC] =3D &t7_sys_gdc.hw, + [CLKID_SYS_DESWARP] =3D &t7_sys_deswarp.hw, + [CLKID_SYS_AMPIPE_NAND] =3D &t7_sys_ampipe_nand.hw, + [CLKID_SYS_AMPIPE_ETH] =3D &t7_sys_ampipe_eth.hw, + [CLKID_SYS_AM2AXI0] =3D &t7_sys_am2axi0.hw, + [CLKID_SYS_AM2AXI1] =3D &t7_sys_am2axi1.hw, + [CLKID_SYS_AM2AXI2] =3D &t7_sys_am2axi2.hw, + [CLKID_SYS_SD_EMMC_A] =3D &t7_sys_sd_emmc_a.hw, + [CLKID_SYS_SD_EMMC_B] =3D &t7_sys_sd_emmc_b.hw, + [CLKID_SYS_SD_EMMC_C] =3D &t7_sys_sd_emmc_c.hw, + [CLKID_SYS_SMARTCARD] =3D &t7_sys_smartcard.hw, + [CLKID_SYS_ACODEC] =3D &t7_sys_acodec.hw, + [CLKID_SYS_SPIFC] =3D &t7_sys_spifc.hw, + [CLKID_SYS_MSR_CLK] =3D &t7_sys_msr_clk.hw, + [CLKID_SYS_IR_CTRL] =3D &t7_sys_ir_ctrl.hw, + [CLKID_SYS_AUDIO] =3D &t7_sys_audio.hw, + [CLKID_SYS_ETH] =3D &t7_sys_eth.hw, + [CLKID_SYS_UART_A] =3D &t7_sys_uart_a.hw, + [CLKID_SYS_UART_B] =3D &t7_sys_uart_b.hw, + [CLKID_SYS_UART_C] =3D &t7_sys_uart_c.hw, + [CLKID_SYS_UART_D] =3D &t7_sys_uart_d.hw, + [CLKID_SYS_UART_E] =3D &t7_sys_uart_e.hw, + [CLKID_SYS_UART_F] =3D &t7_sys_uart_f.hw, + [CLKID_SYS_AIFIFO] =3D &t7_sys_aififo.hw, + [CLKID_SYS_SPICC2] =3D &t7_sys_spicc2.hw, + [CLKID_SYS_SPICC3] =3D &t7_sys_spicc3.hw, + [CLKID_SYS_SPICC4] =3D &t7_sys_spicc4.hw, + [CLKID_SYS_TS_A73] =3D &t7_sys_ts_a73.hw, + [CLKID_SYS_TS_A53] =3D &t7_sys_ts_a53.hw, + [CLKID_SYS_SPICC5] =3D &t7_sys_spicc5.hw, + [CLKID_SYS_G2D] =3D &t7_sys_g2d.hw, + [CLKID_SYS_SPICC0] =3D &t7_sys_spicc0.hw, + [CLKID_SYS_SPICC1] =3D &t7_sys_spicc1.hw, + [CLKID_SYS_PCIE] =3D &t7_sys_pcie.hw, + [CLKID_SYS_USB] =3D &t7_sys_usb.hw, + [CLKID_SYS_PCIE_PHY] =3D &t7_sys_pcie_phy.hw, + [CLKID_SYS_I2C_AO_A] =3D &t7_sys_i2c_ao_a.hw, + [CLKID_SYS_I2C_AO_B] =3D &t7_sys_i2c_ao_b.hw, + [CLKID_SYS_I2C_M_A] =3D &t7_sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] =3D &t7_sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] =3D &t7_sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] =3D &t7_sys_i2c_m_d.hw, + [CLKID_SYS_I2C_M_E] =3D &t7_sys_i2c_m_e.hw, + [CLKID_SYS_I2C_M_F] =3D &t7_sys_i2c_m_f.hw, + [CLKID_SYS_HDMITX_APB] =3D &t7_sys_hdmitx_apb.hw, + [CLKID_SYS_I2C_S_A] =3D &t7_sys_i2c_s_a.hw, + [CLKID_SYS_HDMIRX_PCLK] =3D &t7_sys_hdmirx_pclk.hw, + [CLKID_SYS_MMC_APB] =3D &t7_sys_mmc_apb.hw, + [CLKID_SYS_MIPI_ISP_PCLK] =3D &t7_sys_mipi_isp_pclk.hw, + [CLKID_SYS_RSA] =3D &t7_sys_rsa.hw, + [CLKID_SYS_PCLK_SYS_APB] =3D &t7_sys_pclk_sys_apb.hw, + [CLKID_SYS_A73PCLK_APB] =3D &t7_sys_a73pclk_apb.hw, + [CLKID_SYS_DSPA] =3D &t7_sys_dspa.hw, + [CLKID_SYS_DSPB] =3D &t7_sys_dspb.hw, + [CLKID_SYS_VPU_INTR] =3D &t7_sys_vpu_intr.hw, + [CLKID_SYS_SAR_ADC] =3D &t7_sys_sar_adc.hw, + [CLKID_SYS_GIC] =3D &t7_sys_gic.hw, + [CLKID_SYS_TS_GPU] =3D &t7_sys_ts_gpu.hw, + [CLKID_SYS_TS_NNA] =3D &t7_sys_ts_nna.hw, + [CLKID_SYS_TS_VPU] =3D &t7_sys_ts_vpu.hw, + [CLKID_SYS_TS_HEVC] =3D &t7_sys_ts_hevc.hw, + [CLKID_SYS_PWM_AO_AB] =3D &t7_sys_pwm_ao_ab.hw, + [CLKID_SYS_PWM_AO_CD] =3D &t7_sys_pwm_ao_cd.hw, + [CLKID_SYS_PWM_AO_EF] =3D &t7_sys_pwm_ao_ef.hw, + [CLKID_SYS_PWM_AO_GH] =3D &t7_sys_pwm_ao_gh.hw, + [CLKID_SYS_PWM_AB] =3D &t7_sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] =3D &t7_sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] =3D &t7_sys_pwm_ef.hw, +}; + +static const struct meson_clkc_data t7_peripherals_data =3D { + .hw_clks =3D { + .hws =3D t7_peripherals_hw_clks, + .num =3D ARRAY_SIZE(t7_peripherals_hw_clks), + }, +}; + +static const struct of_device_id t7_peripherals_clkc_match_table[] =3D { + { .compatible =3D "amlogic,t7-peripherals-clkc", .data =3D &t7_peripheral= s_data }, + {} +}; +MODULE_DEVICE_TABLE(of, t7_peripherals_clkc_match_table); + +static struct platform_driver t7_peripherals_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "t7-peripherals-clkc", + .of_match_table =3D t7_peripherals_clkc_match_table, + }, +}; +module_platform_driver(t7_peripherals_clkc_driver); + +MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver"); +MODULE_AUTHOR("Jian Hu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.47.1