During system suspend, if the PCIe link is not up, then there is no need
to broadcast PME_Turn_Off message and wait for L2/L3 transition. So skip
them.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 20c9333bcb1c..8fe3454f3b13 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -1129,6 +1129,9 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
u32 val;
int ret;
+ if (!dw_pcie_link_up(pci))
+ goto stop_link;
+
/*
* If L1SS is supported, then do not put the link into L2 as some
* devices such as NVMe expect low resume latency.
@@ -1162,6 +1165,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
*/
udelay(1);
+stop_link:
dw_pcie_stop_link(pci);
if (pci->pp.ops->deinit)
pci->pp.ops->deinit(&pci->pp);
--
2.48.1
On Wed, 19 Nov 2025 at 19:10, Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> wrote: > > During system suspend, if the PCIe link is not up, then there is no need > to broadcast PME_Turn_Off message and wait for L2/L3 transition. So skip > them. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Tested-by: Vincent Guittot <vincent.guittot@linaro.org> > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 20c9333bcb1c..8fe3454f3b13 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -1129,6 +1129,9 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) > u32 val; > int ret; > > + if (!dw_pcie_link_up(pci)) > + goto stop_link; > + > /* > * If L1SS is supported, then do not put the link into L2 as some > * devices such as NVMe expect low resume latency. > @@ -1162,6 +1165,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) > */ > udelay(1); > > +stop_link: > dw_pcie_stop_link(pci); > if (pci->pp.ops->deinit) > pci->pp.ops->deinit(&pci->pp); > > -- > 2.48.1 >
在 2025/11/20 星期四 2:10, Manivannan Sadhasivam 写道: > During system suspend, if the PCIe link is not up, then there is no need > to broadcast PME_Turn_Off message and wait for L2/L3 transition. So skip > them. > Review-by: Shawn Lin <shawn.lin@rock-chips.com> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 20c9333bcb1c..8fe3454f3b13 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -1129,6 +1129,9 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) > u32 val; > int ret; > > + if (!dw_pcie_link_up(pci)) > + goto stop_link; > + > /* > * If L1SS is supported, then do not put the link into L2 as some > * devices such as NVMe expect low resume latency. > @@ -1162,6 +1165,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) > */ > udelay(1); > > +stop_link: > dw_pcie_stop_link(pci); > if (pci->pp.ops->deinit) > pci->pp.ops->deinit(&pci->pp); >
On Wed, Nov 19, 2025 at 11:40:07PM +0530, Manivannan Sadhasivam wrote: > During system suspend, if the PCIe link is not up, then there is no need > to broadcast PME_Turn_Off message and wait for L2/L3 transition. So skip > them. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> > --- Reviewed-by: Frank Li <Frank.Li@nxp.com> > drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 20c9333bcb1c..8fe3454f3b13 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -1129,6 +1129,9 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) > u32 val; > int ret; > > + if (!dw_pcie_link_up(pci)) > + goto stop_link; > + > /* > * If L1SS is supported, then do not put the link into L2 as some > * devices such as NVMe expect low resume latency. > @@ -1162,6 +1165,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) > */ > udelay(1); > > +stop_link: > dw_pcie_stop_link(pci); > if (pci->pp.ops->deinit) > pci->pp.ops->deinit(&pci->pp); > > -- > 2.48.1 >
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