Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo
MIPI DSI D-PHY" which is required when using single-link LVDS0.
In this mode, the DSI peripheral is not used and the PHY is not
configured for DSI. Instead, the COMBO_PHY_REGx registers are set to
enable LVDS operation.
Enable the PHY driver to work in LVDS mode on chips with a combo D-PHY.
Also change the SUN50I_COMBO_PHY_REG1 macro names to reflect the correct
register name.
Signed-off-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++++-
1 file changed, 68 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 36eab9527..57035b3a4 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -166,8 +166,8 @@
#define SUN50I_COMBO_PHY_REG0_EN_CP BIT(0)
#define SUN50I_COMBO_PHY_REG1 0x114
-#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n) (((n) & 0x7) << 4)
-#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n) ((n) & 0x7)
+#define SUN50I_COMBO_PHY_REG1_REG_VREF1P6(n) (((n) & 0x7) << 4)
+#define SUN50I_COMBO_PHY_REG1_REG_VREF0P8(n) ((n) & 0x7)
#define SUN50I_COMBO_PHY_REG2 0x118
#define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n) ((n) & 0xff)
@@ -181,7 +181,9 @@ struct sun6i_dphy;
struct sun6i_dphy_variant {
void (*tx_power_on)(struct sun6i_dphy *dphy);
+ void (*lvds_power_on)(struct sun6i_dphy *dphy);
bool rx_supported;
+ bool is_combo_dphy;
};
struct sun6i_dphy {
@@ -222,6 +224,18 @@ static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
return 0;
}
+static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct sun6i_dphy *dphy = phy_get_drvdata(phy);
+
+ if (mode == PHY_MODE_LVDS && !dphy->variant->is_combo_dphy) {
+ /* Not a combo D-PHY: LVDS is not supported. */
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
{
u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
@@ -329,6 +343,43 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
udelay(1);
}
+static void sun50i_a100_mipi_dphy_lvds_power_on(struct sun6i_dphy *dphy)
+{
+ regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG1,
+ SUN50I_COMBO_PHY_REG1_REG_VREF1P6(4) |
+ SUN50I_COMBO_PHY_REG1_REG_VREF0P8(3));
+
+ regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
+ SUN50I_COMBO_PHY_REG0_EN_CP);
+ udelay(5);
+
+ regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
+ SUN50I_COMBO_PHY_REG0_EN_LVDS,
+ SUN50I_COMBO_PHY_REG0_EN_LVDS);
+ udelay(5);
+
+ regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
+ SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
+ SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
+ udelay(5);
+
+ regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
+ SUN50I_COMBO_PHY_REG0_EN_MIPI,
+ SUN50I_COMBO_PHY_REG0_EN_MIPI);
+
+ regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
+ SUN6I_DPHY_ANA4_REG_EN_MIPI |
+ SUN6I_DPHY_ANA4_REG_IB(2));
+
+ regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
+ SUN6I_DPHY_ANA3_EN_LDOR |
+ SUN6I_DPHY_ANA3_EN_LDOD);
+
+ regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, 0);
+
+ regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, 0);
+}
+
static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
{
u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
@@ -492,6 +543,13 @@ static int sun6i_dphy_power_on(struct phy *phy)
{
struct sun6i_dphy *dphy = phy_get_drvdata(phy);
+ if (phy->attrs.mode == PHY_MODE_LVDS && dphy->variant->is_combo_dphy) {
+ if (!dphy->variant->lvds_power_on)
+ return -EINVAL;
+ dphy->variant->lvds_power_on(dphy);
+ return 0;
+ }
+
switch (dphy->direction) {
case SUN6I_DPHY_DIRECTION_TX:
return sun6i_dphy_tx_power_on(dphy);
@@ -514,6 +572,11 @@ static int sun6i_dphy_power_off(struct phy *phy)
regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 0);
regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 0);
+ if (phy->attrs.mode == PHY_MODE_LVDS && dphy->variant->is_combo_dphy) {
+ regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG1, 0);
+ regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, 0);
+ }
+
return 0;
}
@@ -533,6 +596,7 @@ static const struct phy_ops sun6i_dphy_ops = {
.configure = sun6i_dphy_configure,
.power_on = sun6i_dphy_power_on,
.power_off = sun6i_dphy_power_off,
+ .set_mode = sun6i_dphy_set_mode,
.init = sun6i_dphy_init,
.exit = sun6i_dphy_exit,
};
@@ -619,6 +683,8 @@ static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = {
.tx_power_on = sun50i_a100_mipi_dphy_tx_power_on,
+ .lvds_power_on = sun50i_a100_mipi_dphy_lvds_power_on,
+ .is_combo_dphy = true,
};
static const struct of_device_id sun6i_dphy_of_table[] = {
--
2.25.1
Dear Kuba,
Thanks for your efforts.
On 11/16/25 2:47 PM, Kuba Szczodrzyński wrote:
> Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo
> MIPI DSI D-PHY" which is required when using single-link LVDS0.
>
> In this mode, the DSI peripheral is not used and the PHY is not
> configured for DSI. Instead, the COMBO_PHY_REGx registers are set to
> enable LVDS operation.
>
> Enable the PHY driver to work in LVDS mode on chips with a combo D-PHY.
>
> Also change the SUN50I_COMBO_PHY_REG1 macro names to reflect the correct
> register name.
>
> Signed-off-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
> ---
> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++++-
> 1 file changed, 68 insertions(+), 2 deletions(-)
I tried integrating your changes in A133 display pipeline and I couldn't get the LVDS working.
Am still narrowing down what is missing in your patch. Driver registration is success and I
can see /dev/fb0 as well. But nothing on the display itself.
But with below changes from my patch,
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 36eab95271b2..d164b2ea5dfd 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -314,13 +314,11 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
/* Disable sigma-delta modulation. */
regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
- regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
- SUN6I_DPHY_ANA4_REG_EN_MIPI,
- SUN6I_DPHY_ANA4_REG_EN_MIPI);
-
regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
+ SUN50I_COMBO_PHY_REG0_EN_LVDS |
SUN50I_COMBO_PHY_REG0_EN_MIPI |
SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
+ SUN50I_COMBO_PHY_REG0_EN_LVDS |
SUN50I_COMBO_PHY_REG0_EN_MIPI |
SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
@@ -528,6 +526,22 @@ static int sun6i_dphy_exit(struct phy *phy)
return 0;
}
LVDS works fine.
Could you please share the diff of your dts / dtsi?
Thanks,
Parthiban
W dniu 2025-11-20 o 07:24:53, Parthiban pisze:
> Dear Kuba,
>
> Thanks for your efforts.
>
> On 11/16/25 2:47 PM, Kuba Szczodrzyński wrote:
>> Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo
>> MIPI DSI D-PHY" which is required when using single-link LVDS0.
>>
>> In this mode, the DSI peripheral is not used and the PHY is not
>> configured for DSI. Instead, the COMBO_PHY_REGx registers are set to
>> enable LVDS operation.
>>
>> Enable the PHY driver to work in LVDS mode on chips with a combo D-PHY.
>>
>> Also change the SUN50I_COMBO_PHY_REG1 macro names to reflect the correct
>> register name.
>>
>> Signed-off-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
>> ---
>> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++++-
>> 1 file changed, 68 insertions(+), 2 deletions(-)
> I tried integrating your changes in A133 display pipeline and I couldn't get the LVDS working.
> Am still narrowing down what is missing in your patch. Driver registration is success and I
> can see /dev/fb0 as well. But nothing on the display itself.
>
> But with below changes from my patch,
>
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 36eab95271b2..d164b2ea5dfd 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -314,13 +314,11 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
> /* Disable sigma-delta modulation. */
> regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
>
> - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
> - SUN6I_DPHY_ANA4_REG_EN_MIPI,
> - SUN6I_DPHY_ANA4_REG_EN_MIPI);
> -
> regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
> + SUN50I_COMBO_PHY_REG0_EN_LVDS |
> SUN50I_COMBO_PHY_REG0_EN_MIPI |
> SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
> + SUN50I_COMBO_PHY_REG0_EN_LVDS |
> SUN50I_COMBO_PHY_REG0_EN_MIPI |
> SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
>
> @@ -528,6 +526,22 @@ static int sun6i_dphy_exit(struct phy *phy)
> return 0;
> }
>
> LVDS works fine.
>
> Could you please share the diff of your dts / dtsi?
Hi,
Here's the DTS overlay I used to enable an LVDS panel on T113. You'll need to adapt the panel specification to your particular display.
I did not need to change the phy driver, so this extra requirement might be specific to A133.
/dts-v1/;
/plugin/;
&{/} {
panel {
compatible = "panel-lvds";
data-mapping = "jeida-18";
ddc-i2c-bus = <&i2c2>;
port {
panel_input: endpoint {
remote-endpoint = <&tcon_lcd0_out_lvds>;
};
};
};
};
&tcon_lcd0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_lvds0_pins>;
};
&tcon_lcd0_out {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_out_lvds: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
Regards
Kuba
>
> Thanks,
> Parthiban
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