From nobody Thu Dec 18 06:01:40 2025 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 454A32EBDD3; Sun, 16 Nov 2025 13:47:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763300859; cv=none; b=EWpoK1JAXj419rymP9/j8KNIiX8hhpWKPkugM3trZEIzvdyNtYlxtBtmz9yvuuqvU2xH175d5ITyFgFibCthFnhSv0NRztkt8ObeZ9sCwOEsHcEUv0q0jrWzZjpl2POqHje1axEQufOdW7F+KpeIPZL11PXi92E3YOmhu9mzrdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763300859; c=relaxed/simple; bh=wOWRPv/XOdIDN3owZwddcqMULZl6LaqXH/Yg6gkLps4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=VTFsTIa59Uu5+HlTA/z4g5k9w8riLUTlTgiW/I2x/RkfELOEx8nf2gbRHkQnEHmenqXNVHHhUkDOupHoNQIz007YikIs+j+2zGQmHTnx3EmhfIPptmB4D1YplPgDnY+/EcnnlfZTRCb5CNt0Zkvz2tXIfHCO3cxqmcYpvTHKqdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl; spf=pass smtp.mailfrom=szczodrzynski.pl; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b=g77wqCNN; arc=none smtp.client-ip=46.242.128.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b="g77wqCNN" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=szczodrzynski.pl; s=x; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=8V4nIdRTsVNfqeRyMcs/OXoQRXmzx7mrofUYormx1Zs=; b=g77wqCNNESZeqa3++6uxQ+Fe8+ FIXu2UKLH2DYJoe5Sk90i6FPRrU8W7l8TfZdr07XU2E3eRsK7awZfN936NW4rJBYWxGTXohwbwEvP GInwN/TogT8DEUPPGhWAaHSOw92m+WQhPP/KPZCVO2AUU11g8c/JJ1u4FrBT/3G+3xPMLw4mJeOuk g5n3NIbJcJTWrzkzzCQ+EMoTPd28ect+I47P6pgxORyZO8p3+WYIR1TCEudx3b0g+LdY4GCBsAlYX qoXaX7u20IbdEGOr9RNvOBSvojn4mkxh5pmBt9DMtWEXXaTeSsoc/VPtSvsX7YfO13tyM7ZuJT0Or h/P42abQ==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1vKd6I-0000000FXMV-1vuQ; Sun, 16 Nov 2025 14:47:30 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, parthiban@linumiz.com, paulk@sys-base.io Subject: [PATCH v3 1/6] phy: allwinner: phy-sun6i-mipi-dphy: Support LVDS in combo D-PHY Date: Sun, 16 Nov 2025 14:47:24 +0100 Message-Id: <20251116134724.447131-1-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251116134609.447043-1-kuba@szczodrzynski.pl> References: <20251116134609.447043-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo MIPI DSI D-PHY" which is required when using single-link LVDS0. In this mode, the DSI peripheral is not used and the PHY is not configured for DSI. Instead, the COMBO_PHY_REGx registers are set to enable LVDS operation. Enable the PHY driver to work in LVDS mode on chips with a combo D-PHY. Also change the SUN50I_COMBO_PHY_REG1 macro names to reflect the correct register name. Signed-off-by: Kuba Szczodrzy=C5=84ski --- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++++- 1 file changed, 68 insertions(+), 2 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allw= inner/phy-sun6i-mipi-dphy.c index 36eab9527..57035b3a4 100644 --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c @@ -166,8 +166,8 @@ #define SUN50I_COMBO_PHY_REG0_EN_CP BIT(0) =20 #define SUN50I_COMBO_PHY_REG1 0x114 -#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n) (((n) & 0x7) << 4) -#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n) ((n) & 0x7) +#define SUN50I_COMBO_PHY_REG1_REG_VREF1P6(n) (((n) & 0x7) << 4) +#define SUN50I_COMBO_PHY_REG1_REG_VREF0P8(n) ((n) & 0x7) =20 #define SUN50I_COMBO_PHY_REG2 0x118 #define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n) ((n) & 0xff) @@ -181,7 +181,9 @@ struct sun6i_dphy; =20 struct sun6i_dphy_variant { void (*tx_power_on)(struct sun6i_dphy *dphy); + void (*lvds_power_on)(struct sun6i_dphy *dphy); bool rx_supported; + bool is_combo_dphy; }; =20 struct sun6i_dphy { @@ -222,6 +224,18 @@ static int sun6i_dphy_configure(struct phy *phy, union= phy_configure_opts *opts) return 0; } =20 +static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int su= bmode) +{ + struct sun6i_dphy *dphy =3D phy_get_drvdata(phy); + + if (mode =3D=3D PHY_MODE_LVDS && !dphy->variant->is_combo_dphy) { + /* Not a combo D-PHY: LVDS is not supported. */ + return -EINVAL; + } + + return 0; +} + static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) { u8 lanes_mask =3D GENMASK(dphy->config.lanes - 1, 0); @@ -329,6 +343,43 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct s= un6i_dphy *dphy) udelay(1); } =20 +static void sun50i_a100_mipi_dphy_lvds_power_on(struct sun6i_dphy *dphy) +{ + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG1, + SUN50I_COMBO_PHY_REG1_REG_VREF1P6(4) | + SUN50I_COMBO_PHY_REG1_REG_VREF0P8(3)); + + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_CP); + udelay(5); + + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_LVDS, + SUN50I_COMBO_PHY_REG0_EN_LVDS); + udelay(5); + + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_COMBOLDO, + SUN50I_COMBO_PHY_REG0_EN_COMBOLDO); + udelay(5); + + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_MIPI, + SUN50I_COMBO_PHY_REG0_EN_MIPI); + + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, + SUN6I_DPHY_ANA4_REG_EN_MIPI | + SUN6I_DPHY_ANA4_REG_IB(2)); + + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, + SUN6I_DPHY_ANA3_EN_LDOR | + SUN6I_DPHY_ANA3_EN_LDOD); + + regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, 0); + + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, 0); +} + static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) { u8 lanes_mask =3D GENMASK(dphy->config.lanes - 1, 0); @@ -492,6 +543,13 @@ static int sun6i_dphy_power_on(struct phy *phy) { struct sun6i_dphy *dphy =3D phy_get_drvdata(phy); =20 + if (phy->attrs.mode =3D=3D PHY_MODE_LVDS && dphy->variant->is_combo_dphy)= { + if (!dphy->variant->lvds_power_on) + return -EINVAL; + dphy->variant->lvds_power_on(dphy); + return 0; + } + switch (dphy->direction) { case SUN6I_DPHY_DIRECTION_TX: return sun6i_dphy_tx_power_on(dphy); @@ -514,6 +572,11 @@ static int sun6i_dphy_power_off(struct phy *phy) regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 0); regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 0); =20 + if (phy->attrs.mode =3D=3D PHY_MODE_LVDS && dphy->variant->is_combo_dphy)= { + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG1, 0); + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, 0); + } + return 0; } =20 @@ -533,6 +596,7 @@ static const struct phy_ops sun6i_dphy_ops =3D { .configure =3D sun6i_dphy_configure, .power_on =3D sun6i_dphy_power_on, .power_off =3D sun6i_dphy_power_off, + .set_mode =3D sun6i_dphy_set_mode, .init =3D sun6i_dphy_init, .exit =3D sun6i_dphy_exit, }; @@ -619,6 +683,8 @@ static const struct sun6i_dphy_variant sun6i_a31_mipi_d= phy_variant =3D { =20 static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant =3D { .tx_power_on =3D sun50i_a100_mipi_dphy_tx_power_on, + .lvds_power_on =3D sun50i_a100_mipi_dphy_lvds_power_on, + .is_combo_dphy =3D true, }; =20 static const struct of_device_id sun6i_dphy_of_table[] =3D { --=20 2.25.1