.../display/allwinner,sun4i-a10-tcon.yaml | 6 ++ .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++ drivers/gpu/drm/sun4i/sun4i_tcon.c | 50 +++++++++++++ drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++- 5 files changed, 141 insertions(+), 2 deletions(-)
[replying to v1 to keep the same series on Patchwork] Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo MIPI DSI D-PHY" which is required when using single-link LVDS0. The same PD0..PD9 pins are used for either DSI or LVDS. Other than having to use the combo D-PHY, LVDS output is configured in the same way as on older chips. This series enables the sun6i MIPI D-PHY to also work in LVDS mode. It is then configured by the LCD TCON, which allows connecting a single-link LVDS display panel. Changes in v2/v3: - Applied code formatting changes from review comments - Changed "dphy" to "combo-phy" - Made the LVDS setup/teardown functions abort early in case of error (adding a proper return value would require changes in several levels of caller functions; perhaps could be done in a separate patch) - Added the PHY properties to DT bindings - Renamed lvds0_pins to lcd_lvds0_pins - Rebased on top of drm/misc/kernel/for-linux-next - Hopefully corrected the incomplete patch list of v2, which happened due to an SMTP error Kuba Szczodrzyński (6): phy: allwinner: phy-sun6i-mipi-dphy: Support LVDS in combo D-PHY drm/sun4i: Support LVDS using MIPI DSI combo D-PHY drm/sun4i: Enable LVDS output on sun20i D1s/T113 dt-bindings: display: sun4i: Add D1s/T113 combo D-PHY bindings riscv: dts: allwinner: d1s-t113: Add D-PHY to TCON LCD0 riscv: dts: allwinner: d1s-t113: Add LVDS0 pins .../display/allwinner,sun4i-a10-tcon.yaml | 6 ++ .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++ drivers/gpu/drm/sun4i/sun4i_tcon.c | 50 +++++++++++++ drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++- 5 files changed, 141 insertions(+), 2 deletions(-) -- 2.25.1
On Sun, Nov 16, 2025 at 9:46 PM Kuba Szczodrzyński <kuba@szczodrzynski.pl> wrote: > > [replying to v1 to keep the same series on Patchwork] That is not the right way to do it. If you reply to an old series, the tooling does not pickup the new version as a separate series. ChenYu > Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo > MIPI DSI D-PHY" which is required when using single-link LVDS0. The same > PD0..PD9 pins are used for either DSI or LVDS. > > Other than having to use the combo D-PHY, LVDS output is configured in > the same way as on older chips. > > This series enables the sun6i MIPI D-PHY to also work in LVDS mode. It > is then configured by the LCD TCON, which allows connecting a > single-link LVDS display panel. > > Changes in v2/v3: > - Applied code formatting changes from review comments > - Changed "dphy" to "combo-phy" > - Made the LVDS setup/teardown functions abort early in case of error > (adding a proper return value would require changes in several levels > of caller functions; perhaps could be done in a separate patch) > - Added the PHY properties to DT bindings > - Renamed lvds0_pins to lcd_lvds0_pins > - Rebased on top of drm/misc/kernel/for-linux-next > - Hopefully corrected the incomplete patch list of v2, which happened > due to an SMTP error > > Kuba Szczodrzyński (6): > phy: allwinner: phy-sun6i-mipi-dphy: Support LVDS in combo D-PHY > drm/sun4i: Support LVDS using MIPI DSI combo D-PHY > drm/sun4i: Enable LVDS output on sun20i D1s/T113 > dt-bindings: display: sun4i: Add D1s/T113 combo D-PHY bindings > riscv: dts: allwinner: d1s-t113: Add D-PHY to TCON LCD0 > riscv: dts: allwinner: d1s-t113: Add LVDS0 pins > > .../display/allwinner,sun4i-a10-tcon.yaml | 6 ++ > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++ > drivers/gpu/drm/sun4i/sun4i_tcon.c | 50 +++++++++++++ > drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++ > drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++- > 5 files changed, 141 insertions(+), 2 deletions(-) > > -- > 2.25.1 >
W dniu 2025-11-16 o 15:03:18, Chen-Yu Tsai pisze: > On Sun, Nov 16, 2025 at 9:46 PM Kuba Szczodrzyński > <kuba@szczodrzynski.pl> wrote: >> [replying to v1 to keep the same series on Patchwork] > That is not the right way to do it. > > If you reply to an old series, the tooling does not pickup the new version > as a separate series. > > ChenYu Hi, I noticed that it indeed didn't work. However, Patchwork didn't pick up the v2 cover letter at all, so I thought replying to v2 would mess up the thread even more. That being said, the v3 cover letter is not visible there either. Should I resend this as v4 [which message to reply to?] or send a completely new series perhaps? I apologize for the confusion, this is my first time doing that. Regards Kuba >> Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo >> MIPI DSI D-PHY" which is required when using single-link LVDS0. The same >> PD0..PD9 pins are used for either DSI or LVDS. >> >> Other than having to use the combo D-PHY, LVDS output is configured in >> the same way as on older chips. >> >> This series enables the sun6i MIPI D-PHY to also work in LVDS mode. It >> is then configured by the LCD TCON, which allows connecting a >> single-link LVDS display panel. >> >> Changes in v2/v3: >> - Applied code formatting changes from review comments >> - Changed "dphy" to "combo-phy" >> - Made the LVDS setup/teardown functions abort early in case of error >> (adding a proper return value would require changes in several levels >> of caller functions; perhaps could be done in a separate patch) >> - Added the PHY properties to DT bindings >> - Renamed lvds0_pins to lcd_lvds0_pins >> - Rebased on top of drm/misc/kernel/for-linux-next >> - Hopefully corrected the incomplete patch list of v2, which happened >> due to an SMTP error >> >> Kuba Szczodrzyński (6): >> phy: allwinner: phy-sun6i-mipi-dphy: Support LVDS in combo D-PHY >> drm/sun4i: Support LVDS using MIPI DSI combo D-PHY >> drm/sun4i: Enable LVDS output on sun20i D1s/T113 >> dt-bindings: display: sun4i: Add D1s/T113 combo D-PHY bindings >> riscv: dts: allwinner: d1s-t113: Add D-PHY to TCON LCD0 >> riscv: dts: allwinner: d1s-t113: Add LVDS0 pins >> >> .../display/allwinner,sun4i-a10-tcon.yaml | 6 ++ >> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++ >> drivers/gpu/drm/sun4i/sun4i_tcon.c | 50 +++++++++++++ >> drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++ >> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++- >> 5 files changed, 141 insertions(+), 2 deletions(-) >> >> -- >> 2.25.1 >>
On Sun, Nov 16, 2025 at 10:31 PM Kuba Szczodrzyński <kuba@szczodrzynski.pl> wrote: > > W dniu 2025-11-16 o 15:03:18, Chen-Yu Tsai pisze: > > > On Sun, Nov 16, 2025 at 9:46 PM Kuba Szczodrzyński > > <kuba@szczodrzynski.pl> wrote: > >> [replying to v1 to keep the same series on Patchwork] > > That is not the right way to do it. > > > > If you reply to an old series, the tooling does not pickup the new version > > as a separate series. > > > > ChenYu > > Hi, > > I noticed that it indeed didn't work. However, Patchwork didn't pick up the v2 cover letter at all, so I thought replying to v2 would mess up the thread even more. > > That being said, the v3 cover letter is not visible there either. > > Should I resend this as v4 [which message to reply to?] or send a completely new series perhaps? Each new version should be a completely new series. If patchwork still didn't pick it up, then it's possible either your patches didn't reach the mailing lists or the patchwork instances. Please check lore to see if your patches are there. ChenYu > I apologize for the confusion, this is my first time doing that. > > Regards > Kuba > > >> Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo > >> MIPI DSI D-PHY" which is required when using single-link LVDS0. The same > >> PD0..PD9 pins are used for either DSI or LVDS. > >> > >> Other than having to use the combo D-PHY, LVDS output is configured in > >> the same way as on older chips. > >> > >> This series enables the sun6i MIPI D-PHY to also work in LVDS mode. It > >> is then configured by the LCD TCON, which allows connecting a > >> single-link LVDS display panel. > >> > >> Changes in v2/v3: > >> - Applied code formatting changes from review comments > >> - Changed "dphy" to "combo-phy" > >> - Made the LVDS setup/teardown functions abort early in case of error > >> (adding a proper return value would require changes in several levels > >> of caller functions; perhaps could be done in a separate patch) > >> - Added the PHY properties to DT bindings > >> - Renamed lvds0_pins to lcd_lvds0_pins > >> - Rebased on top of drm/misc/kernel/for-linux-next > >> - Hopefully corrected the incomplete patch list of v2, which happened > >> due to an SMTP error > >> > >> Kuba Szczodrzyński (6): > >> phy: allwinner: phy-sun6i-mipi-dphy: Support LVDS in combo D-PHY > >> drm/sun4i: Support LVDS using MIPI DSI combo D-PHY > >> drm/sun4i: Enable LVDS output on sun20i D1s/T113 > >> dt-bindings: display: sun4i: Add D1s/T113 combo D-PHY bindings > >> riscv: dts: allwinner: d1s-t113: Add D-PHY to TCON LCD0 > >> riscv: dts: allwinner: d1s-t113: Add LVDS0 pins > >> > >> .../display/allwinner,sun4i-a10-tcon.yaml | 6 ++ > >> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++ > >> drivers/gpu/drm/sun4i/sun4i_tcon.c | 50 +++++++++++++ > >> drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++ > >> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++- > >> 5 files changed, 141 insertions(+), 2 deletions(-) > >> > >> -- > >> 2.25.1 > >> >
W dniu 2025-11-16 o 15:37:15, Chen-Yu Tsai pisze: > On Sun, Nov 16, 2025 at 10:31 PM Kuba Szczodrzyński > <kuba@szczodrzynski.pl> wrote: >> W dniu 2025-11-16 o 15:03:18, Chen-Yu Tsai pisze: >> >>> On Sun, Nov 16, 2025 at 9:46 PM Kuba Szczodrzyński >>> <kuba@szczodrzynski.pl> wrote: >>>> [replying to v1 to keep the same series on Patchwork] >>> That is not the right way to do it. >>> >>> If you reply to an old series, the tooling does not pickup the new version >>> as a separate series. >>> >>> ChenYu >> Hi, >> >> I noticed that it indeed didn't work. However, Patchwork didn't pick up the v2 cover letter at all, so I thought replying to v2 would mess up the thread even more. >> >> That being said, the v3 cover letter is not visible there either. >> >> Should I resend this as v4 [which message to reply to?] or send a completely new series perhaps? > Each new version should be a completely new series. > > If patchwork still didn't pick it up, then it's possible either your > patches didn't reach the mailing lists or the patchwork instances. > Please check lore to see if your patches are there. The patches are on lore, but patchwork didn't pick them up because some were sent with the wrong In-Reply-To header, and that created threading issues. Assuming I understood your reply correctly, I'll send the entire series as v4 *without* the In-Reply-To header, which will create a new series on patchwork. Regards Kuba > > ChenYu > >> I apologize for the confusion, this is my first time doing that. >> >> Regards >> Kuba >> >>>> Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo >>>> MIPI DSI D-PHY" which is required when using single-link LVDS0. The same >>>> PD0..PD9 pins are used for either DSI or LVDS. >>>> >>>> Other than having to use the combo D-PHY, LVDS output is configured in >>>> the same way as on older chips. >>>> >>>> This series enables the sun6i MIPI D-PHY to also work in LVDS mode. It >>>> is then configured by the LCD TCON, which allows connecting a >>>> single-link LVDS display panel. >>>> >>>> Changes in v2/v3: >>>> - Applied code formatting changes from review comments >>>> - Changed "dphy" to "combo-phy" >>>> - Made the LVDS setup/teardown functions abort early in case of error >>>> (adding a proper return value would require changes in several levels >>>> of caller functions; perhaps could be done in a separate patch) >>>> - Added the PHY properties to DT bindings >>>> - Renamed lvds0_pins to lcd_lvds0_pins >>>> - Rebased on top of drm/misc/kernel/for-linux-next >>>> - Hopefully corrected the incomplete patch list of v2, which happened >>>> due to an SMTP error >>>> >>>> Kuba Szczodrzyński (6): >>>> phy: allwinner: phy-sun6i-mipi-dphy: Support LVDS in combo D-PHY >>>> drm/sun4i: Support LVDS using MIPI DSI combo D-PHY >>>> drm/sun4i: Enable LVDS output on sun20i D1s/T113 >>>> dt-bindings: display: sun4i: Add D1s/T113 combo D-PHY bindings >>>> riscv: dts: allwinner: d1s-t113: Add D-PHY to TCON LCD0 >>>> riscv: dts: allwinner: d1s-t113: Add LVDS0 pins >>>> >>>> .../display/allwinner,sun4i-a10-tcon.yaml | 6 ++ >>>> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++ >>>> drivers/gpu/drm/sun4i/sun4i_tcon.c | 50 +++++++++++++ >>>> drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++ >>>> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++- >>>> 5 files changed, 141 insertions(+), 2 deletions(-) >>>> >>>> -- >>>> 2.25.1 >>>>
On 11/16/25 2:46 PM, Kuba Szczodrzyński wrote:
> Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo
> MIPI DSI D-PHY" which is required when using single-link LVDS0. The same
> PD0..PD9 pins are used for either DSI or LVDS.
>
> Other than having to use the combo D-PHY, LVDS output is configured in
> the same way as on older chips.
>
> This series enables the sun6i MIPI D-PHY to also work in LVDS mode. It
> is then configured by the LCD TCON, which allows connecting a
> single-link LVDS display panel.
Also one additional note is, current LVDS implementation in tcon doesn't
handle LVDS mode in "0x0084 LCD LVDS Configure". We have only bitwidth
handled. When using smaller LVDS panels vesa & jeida needs to be handled
separately. Not sure if the mode support bit is same across all the SoC's TCON,
but here is the diff which I have used to make it work for vesa-24 by tweaking
the a133 lvds hook.
commit 1f2d8983f78a11adab759160957a9cf6dc4296aa
Author: Parthiban Nallathambi <parthiban@linumiz.com>
Date: Tue Feb 3 21:55:48 2026 +0530
drm/sunxi: a133 add support for LVDS mode handling
A133 supports both NS and JEIDA mode. Add support depends on the
mode selected from the devicetree data mapping.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 3bacc897217f..98a2fb7ed015 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -175,8 +175,34 @@ static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
static void sun20i_tcon_setup_lvds_dphy(struct sun4i_tcon *tcon,
const struct drm_encoder *encoder)
{
+ struct drm_connector *connector;
+ struct drm_display_info *info;
union phy_configure_opts opts = { };
+ connector = sun4i_tcon_get_connector(encoder);
+ if (!connector)
+ return;
+
+ info = &connector->display_info;
+ if (info->num_bus_formats != 1)
+ return;
+
+ switch (info->bus_formats[0]) {
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ case MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA:
+ regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
+ SUN4I_TCON0_LVDS_IF_MODE,
+ SUN4I_TCON0_LVDS_IF_MODE);
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ case MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG:
+ regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
+ SUN4I_TCON0_LVDS_IF_MODE,
+ 0);
+ break;
+ }
+
if (!tcon->quirks->has_combo_dphy || !tcon->dphy)
return;
@@ -550,7 +576,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
else
reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
- regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
+ regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
+ SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 | SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK,
+ reg);
/* Setup the polarity of the various signals */
if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 7e6a5f500d37..fa45b070def2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -101,11 +101,12 @@
#define SUN4I_TCON0_LVDS_IF_REG 0x84
#define SUN4I_TCON0_LVDS_IF_EN BIT(31)
+#define SUN4I_TCON0_LVDS_IF_MODE BIT(27)
#define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK BIT(26)
#define SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS (1 << 26)
#define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS (0 << 26)
#define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK BIT(20)
-#define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 (1 << 20)
+#define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 BIT(20)
#define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK BIT(4)
#define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL (1 << 4)
#define SUN4I_TCON0_LVDS_IF_CLK_POL_INV (0 << 4)
Shall this be same for all the TCON?
--
Thanks,
Parthiban
https://linumiz.com
https://www.linkedin.com/company/linumiz
© 2016 - 2026 Red Hat, Inc.