From nobody Tue Dec 16 19:46:02 2025 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 454A32EBDD3; Sun, 16 Nov 2025 13:47:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763300859; cv=none; b=EWpoK1JAXj419rymP9/j8KNIiX8hhpWKPkugM3trZEIzvdyNtYlxtBtmz9yvuuqvU2xH175d5ITyFgFibCthFnhSv0NRztkt8ObeZ9sCwOEsHcEUv0q0jrWzZjpl2POqHje1axEQufOdW7F+KpeIPZL11PXi92E3YOmhu9mzrdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763300859; c=relaxed/simple; bh=wOWRPv/XOdIDN3owZwddcqMULZl6LaqXH/Yg6gkLps4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=VTFsTIa59Uu5+HlTA/z4g5k9w8riLUTlTgiW/I2x/RkfELOEx8nf2gbRHkQnEHmenqXNVHHhUkDOupHoNQIz007YikIs+j+2zGQmHTnx3EmhfIPptmB4D1YplPgDnY+/EcnnlfZTRCb5CNt0Zkvz2tXIfHCO3cxqmcYpvTHKqdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl; spf=pass smtp.mailfrom=szczodrzynski.pl; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b=g77wqCNN; arc=none smtp.client-ip=46.242.128.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b="g77wqCNN" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=szczodrzynski.pl; s=x; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=8V4nIdRTsVNfqeRyMcs/OXoQRXmzx7mrofUYormx1Zs=; b=g77wqCNNESZeqa3++6uxQ+Fe8+ FIXu2UKLH2DYJoe5Sk90i6FPRrU8W7l8TfZdr07XU2E3eRsK7awZfN936NW4rJBYWxGTXohwbwEvP GInwN/TogT8DEUPPGhWAaHSOw92m+WQhPP/KPZCVO2AUU11g8c/JJ1u4FrBT/3G+3xPMLw4mJeOuk g5n3NIbJcJTWrzkzzCQ+EMoTPd28ect+I47P6pgxORyZO8p3+WYIR1TCEudx3b0g+LdY4GCBsAlYX qoXaX7u20IbdEGOr9RNvOBSvojn4mkxh5pmBt9DMtWEXXaTeSsoc/VPtSvsX7YfO13tyM7ZuJT0Or h/P42abQ==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1vKd6I-0000000FXMV-1vuQ; Sun, 16 Nov 2025 14:47:30 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, parthiban@linumiz.com, paulk@sys-base.io Subject: [PATCH v3 1/6] phy: allwinner: phy-sun6i-mipi-dphy: Support LVDS in combo D-PHY Date: Sun, 16 Nov 2025 14:47:24 +0100 Message-Id: <20251116134724.447131-1-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251116134609.447043-1-kuba@szczodrzynski.pl> References: <20251116134609.447043-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo MIPI DSI D-PHY" which is required when using single-link LVDS0. In this mode, the DSI peripheral is not used and the PHY is not configured for DSI. Instead, the COMBO_PHY_REGx registers are set to enable LVDS operation. Enable the PHY driver to work in LVDS mode on chips with a combo D-PHY. Also change the SUN50I_COMBO_PHY_REG1 macro names to reflect the correct register name. Signed-off-by: Kuba Szczodrzy=C5=84ski --- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 70 ++++++++++++++++++++- 1 file changed, 68 insertions(+), 2 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allw= inner/phy-sun6i-mipi-dphy.c index 36eab9527..57035b3a4 100644 --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c @@ -166,8 +166,8 @@ #define SUN50I_COMBO_PHY_REG0_EN_CP BIT(0) =20 #define SUN50I_COMBO_PHY_REG1 0x114 -#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n) (((n) & 0x7) << 4) -#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n) ((n) & 0x7) +#define SUN50I_COMBO_PHY_REG1_REG_VREF1P6(n) (((n) & 0x7) << 4) +#define SUN50I_COMBO_PHY_REG1_REG_VREF0P8(n) ((n) & 0x7) =20 #define SUN50I_COMBO_PHY_REG2 0x118 #define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n) ((n) & 0xff) @@ -181,7 +181,9 @@ struct sun6i_dphy; =20 struct sun6i_dphy_variant { void (*tx_power_on)(struct sun6i_dphy *dphy); + void (*lvds_power_on)(struct sun6i_dphy *dphy); bool rx_supported; + bool is_combo_dphy; }; =20 struct sun6i_dphy { @@ -222,6 +224,18 @@ static int sun6i_dphy_configure(struct phy *phy, union= phy_configure_opts *opts) return 0; } =20 +static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int su= bmode) +{ + struct sun6i_dphy *dphy =3D phy_get_drvdata(phy); + + if (mode =3D=3D PHY_MODE_LVDS && !dphy->variant->is_combo_dphy) { + /* Not a combo D-PHY: LVDS is not supported. */ + return -EINVAL; + } + + return 0; +} + static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) { u8 lanes_mask =3D GENMASK(dphy->config.lanes - 1, 0); @@ -329,6 +343,43 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct s= un6i_dphy *dphy) udelay(1); } =20 +static void sun50i_a100_mipi_dphy_lvds_power_on(struct sun6i_dphy *dphy) +{ + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG1, + SUN50I_COMBO_PHY_REG1_REG_VREF1P6(4) | + SUN50I_COMBO_PHY_REG1_REG_VREF0P8(3)); + + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_CP); + udelay(5); + + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_LVDS, + SUN50I_COMBO_PHY_REG0_EN_LVDS); + udelay(5); + + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_COMBOLDO, + SUN50I_COMBO_PHY_REG0_EN_COMBOLDO); + udelay(5); + + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_MIPI, + SUN50I_COMBO_PHY_REG0_EN_MIPI); + + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, + SUN6I_DPHY_ANA4_REG_EN_MIPI | + SUN6I_DPHY_ANA4_REG_IB(2)); + + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, + SUN6I_DPHY_ANA3_EN_LDOR | + SUN6I_DPHY_ANA3_EN_LDOD); + + regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, 0); + + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, 0); +} + static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) { u8 lanes_mask =3D GENMASK(dphy->config.lanes - 1, 0); @@ -492,6 +543,13 @@ static int sun6i_dphy_power_on(struct phy *phy) { struct sun6i_dphy *dphy =3D phy_get_drvdata(phy); =20 + if (phy->attrs.mode =3D=3D PHY_MODE_LVDS && dphy->variant->is_combo_dphy)= { + if (!dphy->variant->lvds_power_on) + return -EINVAL; + dphy->variant->lvds_power_on(dphy); + return 0; + } + switch (dphy->direction) { case SUN6I_DPHY_DIRECTION_TX: return sun6i_dphy_tx_power_on(dphy); @@ -514,6 +572,11 @@ static int sun6i_dphy_power_off(struct phy *phy) regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 0); regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 0); =20 + if (phy->attrs.mode =3D=3D PHY_MODE_LVDS && dphy->variant->is_combo_dphy)= { + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG1, 0); + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, 0); + } + return 0; } =20 @@ -533,6 +596,7 @@ static const struct phy_ops sun6i_dphy_ops =3D { .configure =3D sun6i_dphy_configure, .power_on =3D sun6i_dphy_power_on, .power_off =3D sun6i_dphy_power_off, + .set_mode =3D sun6i_dphy_set_mode, .init =3D sun6i_dphy_init, .exit =3D sun6i_dphy_exit, }; @@ -619,6 +683,8 @@ static const struct sun6i_dphy_variant sun6i_a31_mipi_d= phy_variant =3D { =20 static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant =3D { .tx_power_on =3D sun50i_a100_mipi_dphy_tx_power_on, + .lvds_power_on =3D sun50i_a100_mipi_dphy_lvds_power_on, + .is_combo_dphy =3D true, }; =20 static const struct of_device_id sun6i_dphy_of_table[] =3D { --=20 2.25.1 From nobody Tue Dec 16 19:46:02 2025 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48DF42EAB6E; Sun, 16 Nov 2025 13:48:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763300914; cv=none; b=YrDZnGhJM3zZ9QjP+0Kju5W79f2anktnTA/ffMwllJb4/2I1NWtMFPeWEBokUYQCNdAUlxKX9sksfQSxbBtCDFkwQ9spvV0uipY+gpqdjH4QX+DEfTdRUfU6xj7wJOtSYeIuNK+1JzA70+XK5tqMTQrzCu4BwH6EEjsW+31GRMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763300914; c=relaxed/simple; bh=fz8fUcTjwBz+58mze8lroRkBxKWZWRoYijIJuiuabfU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=Vz+AZkbaqsTmfTh6XWW9JQYr88rsjFCNf1dD2iYh76ZJZ7GEoJsHY6EFhPKnzlOVZtghh78SzlQI4qPeZFsH1yRQrFKe/UA9rgoSP/WorpAN4GcEsQOstwk0La74NPn5b2S/3u1CKNPNU05s9Z44Fb4QfezREO6LscMcLacSNww= ARC-Authentication-Results: i=1; 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bh=AnluJ6Mta9yYcmtq3aOb9bOnNMSPyiKv709+YjBCRsY=; b=vmNalNjfG+z3PNdpOoQ5ip9Eas 7XMmR+waCSwCZOHwa6EECAbFYPGNTicbyAkCAAasLQTeNDRmPkUxO1vJ/lNQbSQ3YAc2fdIUAAjDa k5lMuc3LuK1ioLmUz1xM490yb0CnRKcgwkqF1kKVU8fsRZrRLR4jxKDh+A0HxrCvu2bJwk6M/ok9q DxVa934oFRRjsas1CDniLrbmQakKsb6VxRcHfrhkIGNiosZ/uVQEMySntgDuAjTPpKJmuk3HZ/6yo sC60wT6EOb1PdXaoJeJ+RWj4nsekYAaGab09cKt7IVu5cB1x+pcI+h6oSeU5Q53FSksx9tNx7KFSR wN1Gc8hg==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1vKd7C-0000000FXPA-2jbh; Sun, 16 Nov 2025 14:48:26 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, parthiban@linumiz.com, paulk@sys-base.io Subject: [PATCH v3 2/6] drm/sun4i: Support LVDS using MIPI DSI combo D-PHY Date: Sun, 16 Nov 2025 14:48:21 +0100 Message-Id: <20251116134821.447272-1-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251116134609.447043-1-kuba@szczodrzynski.pl> References: <20251116134609.447043-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl On Allwinner chips with a combo D-PHY, the TCON LCD0 should fetch it from device tree in order to enable LVDS. Since the PHY also needs to be powered off to disable LVDS, add a function to the quirks. Signed-off-by: Kuba Szczodrzy=C5=84ski --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 12 ++++++++++++ drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun= 4i_tcon.c index 960e83c82..247400785 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -183,6 +184,8 @@ static void sun4i_tcon_lvds_set_status(struct sun4i_tco= n *tcon, } else { regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, 0); + if (tcon->quirks->teardown_lvds_phy) + tcon->quirks->teardown_lvds_phy(tcon, encoder); } } =20 @@ -1245,6 +1248,15 @@ static int sun4i_tcon_bind(struct device *dev, struc= t device *master, goto err_free_dclk; } =20 + if (tcon->quirks->has_combo_dphy) { + tcon->dphy =3D devm_phy_get(dev, "combo-phy"); + if (IS_ERR(tcon->dphy)) { + dev_err(dev, "Couldn't get the combo D-PHY\n"); + ret =3D PTR_ERR(tcon->dphy); + goto err_free_dclk; + } + } + if (tcon->quirks->has_channel_0) { /* * If we have an LVDS panel connected to the TCON, we should diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun= 4i_tcon.h index fa23aa23f..82b65a2e6 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -239,6 +239,7 @@ struct sun4i_tcon_quirks { bool has_channel_0; /* a83t does not have channel 0 on second TCON */ bool has_channel_1; /* a33 does not have channel 1 */ bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TC= ON clock? */ + bool has_combo_dphy; /* Is the D-PHY used for LVDS output? */ bool needs_de_be_mux; /* sun6i needs mux to select backend */ bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */ bool supports_lvds; /* Does the TCON support an LVDS output? */ @@ -250,6 +251,8 @@ struct sun4i_tcon_quirks { /* handler for LVDS setup routine */ void (*setup_lvds_phy)(struct sun4i_tcon *tcon, const struct drm_encoder *encoder); + void (*teardown_lvds_phy)(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder); }; =20 struct sun4i_tcon { @@ -282,6 +285,9 @@ struct sun4i_tcon { /* Associated crtc */ struct sun4i_crtc *crtc; =20 + /* Associated D-PHY */ + struct phy *dphy; + int id; =20 /* TCON list management */ --=20 2.25.1 From nobody Tue Dec 16 19:46:02 2025 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 249E82D838B; Sun, 16 Nov 2025 13:48:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763300931; cv=none; b=tngT7mhUTYvOBK+K8lyWZu2yCB418B5CQkpkybHLrn/+kcVCyLFMNTzuS2ZI5Ks+wvlD2UnsQfCs6+A9K3idSEfv4C2jDNvboBj9kIK+OfQ2WYCdTZhOzKVwN+T7fl2Fnvm8Nsu7AQ8v5OTRBJa8XNY8c2CjyL0gPwVaMJcCL3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763300931; c=relaxed/simple; bh=TEr+ujnpLZapoxLfzFbhpfSVZDeusyh2Iu9mSJzQzWA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=qrbHDORONUVEUiQWdFL3Zb9a0grcrHaC70uzGZ647wqXecDe3bj5J/EfZ2NNRxPkDSRx/S7rmxxcJ/9n0GLc510ebei7VcVYFydKFiOa/uiZKQi9VbGZTbIk1qzBCwLOGwQnDNU8psB/+kId+GaqOjtaCMl/0EImHI8jREq18s4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl; spf=pass smtp.mailfrom=szczodrzynski.pl; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b=uM3oxU8f; arc=none smtp.client-ip=46.242.128.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b="uM3oxU8f" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=szczodrzynski.pl; s=x; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=xsxQS9uMu2ulj3kK3D36meG/HO1FCmilYNNF+TdhSOQ=; b=uM3oxU8f2UEcgSSoKB30Yri+pI qxJkxjqM8QzxIg/gUJTG7m+7XkqL0APmwByGqRbNF9Hc1inYgAa7y+cQrmniRs/8dA3g601Rzhinn ml3/LANfdSZDo//IUPNcf6FqRXoPCHrWeHBfB0tHuQJcNqFEYOnWjgSRrGCGayOTcqfejxXq7Hcz3 kkcELdrGdtOEe0pTNcMUFNYHYyY5W2JuDgUYyytx+3IaShchEHfpdkX9GL4XzJe+vgIs5ED1PzUlT RTMJr87j/D0aLEFpZoL1x2yEd8xeS5/DbdFYSfzxtR0izAi1oqlyUK0gUT4M6kjA7UW345KUqgxRP 1KHdbRyw==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1vKd7P-0000000FXPf-0iOX; Sun, 16 Nov 2025 14:48:39 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, parthiban@linumiz.com, paulk@sys-base.io Subject: [PATCH v3 3/6] drm/sun4i: Enable LVDS output on sun20i D1s/T113 Date: Sun, 16 Nov 2025 14:48:35 +0100 Message-Id: <20251116134835.447357-1-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251116134609.447043-1-kuba@szczodrzynski.pl> References: <20251116134609.447043-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl The Allwinner D1s/T113 needs to use the combo D-PHY to enable LVDS output. Enable LVDS support in the TCON and configure it using the PHY. Abort PHY setup/teardown early if it fails. Signed-off-by: Kuba Szczodrzy=C5=84ski --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 38 ++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun= 4i_tcon.c index 247400785..e072ecc6d 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -171,6 +171,40 @@ static void sun6i_tcon_setup_lvds_phy(struct sun4i_tco= n *tcon, SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); } =20 +static void sun20i_tcon_setup_lvds_dphy(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder) +{ + union phy_configure_opts opts =3D { }; + + if (!tcon->quirks->has_combo_dphy || !tcon->dphy) + return; + + if (phy_init(tcon->dphy)) + return; + + if (phy_set_mode(tcon->dphy, PHY_MODE_LVDS)) + return; + + if (phy_configure(tcon->dphy, &opts)) + return; + + if (phy_power_on(tcon->dphy)) + return; +} + +static void sun20i_tcon_teardown_lvds_dphy(struct sun4i_tcon *tcon, + const struct drm_encoder *encoder) +{ + if (!tcon->quirks->has_combo_dphy || !tcon->dphy) + return; + + if (phy_power_off(tcon->dphy)) + return; + + if (phy_exit(tcon->dphy)) + return; +} + static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, const struct drm_encoder *encoder, bool enabled) @@ -1550,8 +1584,12 @@ static const struct sun4i_tcon_quirks sun9i_a80_tcon= _tv_quirks =3D { =20 static const struct sun4i_tcon_quirks sun20i_d1_lcd_quirks =3D { .has_channel_0 =3D true, + .has_combo_dphy =3D true, + .supports_lvds =3D true, .dclk_min_div =3D 1, .set_mux =3D sun8i_r40_tcon_tv_set_mux, + .setup_lvds_phy =3D sun20i_tcon_setup_lvds_dphy, + .teardown_lvds_phy =3D sun20i_tcon_teardown_lvds_dphy, }; =20 /* sun4i_drv uses this list to check if a device node is a TCON */ --=20 2.25.1 From nobody Tue Dec 16 19:46:02 2025 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CC6D2F7ABC; Sun, 16 Nov 2025 13:49:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1vKd8W-0000000FXUh-2saU; Sun, 16 Nov 2025 14:49:48 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, parthiban@linumiz.com, paulk@sys-base.io Subject: [PATCH v3 4/6] dt-bindings: display: sun4i: Add D1s/T113 combo D-PHY bindings Date: Sun, 16 Nov 2025 14:49:43 +0100 Message-Id: <20251116134943.447443-1-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251116134609.447043-1-kuba@szczodrzynski.pl> References: <20251116134609.447043-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl The sun4i TCON needs a reference to the D-PHY in order to support LVDS on Allwinner D1s/T113. Add phys and phy-names to DT bindings. Signed-off-by: Kuba Szczodrzy=C5=84ski --- .../bindings/display/allwinner,sun4i-a10-tcon.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-= tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-t= con.yaml index 724d93b91..52589341f 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.ya= ml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.ya= ml @@ -115,6 +115,12 @@ properties: - const: edp - const: lvds =20 + phys: + maxItems: 1 + + phy-names: + const: combo-phy + ports: $ref: /schemas/graph.yaml#/properties/ports =20 --=20 2.25.1 From nobody Tue Dec 16 19:46:02 2025 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E54762F6560; Sun, 16 Nov 2025 13:50:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763301018; cv=none; b=rje5Z1gfY+67h3EVjYnyBxgp8HUl7YXCzBKFIU6FGNC4U5tpkikFkqA1dxaX1Mglomk6DFIEYiPjdbh7cqE6vVQMUgZyzuHCM05+CfPw0jWe6tVVbIQgRTT0zoCypQqtnfbIB5u3hhw3+nUfqOjUK5kAgcp1lHQptrfk37ii4Oc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763301018; c=relaxed/simple; bh=g47VNxOuIRVfIjJ9Gd6MyaohN5b5SV9VKZlky0fDxHc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=SS2Z3+vl+6joNrF9tVN/mkzsEtEg5Ig6f0SH4iv4VzbqzdvSvGoa4UmI0F0z7giDkwhzRZlZBJVosDe9HdNG18V1348lN31TM+WFVNaHMlfZZ6NtbQQ52l5FwIP27rN6mHygzSFmY8LoZAhvcWLe49AtI1YSwSPppQdookXbKDw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl; spf=pass smtp.mailfrom=szczodrzynski.pl; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b=Gg+j1iN2; arc=none smtp.client-ip=46.242.128.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b="Gg+j1iN2" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=szczodrzynski.pl; s=x; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=BPO9NrD7t7ozHNmv9SwKBa5YjnO0HgIRT0temEkfh70=; b=Gg+j1iN23n1xHJQNAyHu8/3ZYX XvHAhG3jyG1PpNQAeLFit19IsBKmN86Nb2Zyj5mlmQkN2/V005zWuP9lJbWs5szW7dntwRKci25Xc c86GTd+4URPW9Mo7oXm5Sfkv8k8oY7nGo8rMz1N0tUjMYdn9vdkMweUcgWvaIVAvQHK9tYfGnUX94 bXBBYvqTqs9NayEiTXczKmSDDVG3UFmu6qGReiG59Z6aVEj0iNS4ri6YivZmggmB67Nw9jVLEwHhQ JRi/6HGoJ6M6S92GuxSn3ccsNEg1WnZLCse3sTRbfjw8AUN/t95E8QktjTbPWLOUtP7h9KbunJBhd wuHQycew==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1vKd8k-0000000FXVf-3tGq; Sun, 16 Nov 2025 14:50:03 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, parthiban@linumiz.com, paulk@sys-base.io Subject: [PATCH v3 5/6] riscv: dts: allwinner: d1s-t113: Add D-PHY to TCON LCD0 Date: Sun, 16 Nov 2025 14:49:57 +0100 Message-Id: <20251116134957.447529-1-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251116134609.447043-1-kuba@szczodrzynski.pl> References: <20251116134609.447043-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl The sun4i TCON needs a reference to the D-PHY in order to support LVDS on Allwinner D1s/T113. Add phys and phy-names to sunxi-d1s-t113 common device tree. Signed-off-by: Kuba Szczodrzy=C5=84ski --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi index 63e252b44..78aa61607 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -876,6 +876,8 @@ tcon_lcd0: lcd-controller@5461000 { resets =3D <&ccu RST_BUS_TCON_LCD0>, <&ccu RST_BUS_LVDS0>; reset-names =3D "lcd", "lvds"; + phys =3D <&dphy>; + phy-names =3D "combo-phy"; #clock-cells =3D <0>; =20 ports { --=20 2.25.1 From nobody Tue Dec 16 19:46:02 2025 Received: from s2.avantea.pl (s2.avantea.pl [46.242.128.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E60082F39BE; Sun, 16 Nov 2025 13:50:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.242.128.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763301047; cv=none; b=AdIl0O63cDULoI6KSWKCGqAxL3XTJ+Lr7SJPZFmg2v0LlWXf88BxgOSqbjFJI+ftlv/LbIovqsmsS5giwG1SSdrc2ffJgadg/J+NAELiLZ0c91CAawz6xXLt8K4NXU7r8Oj7eVMvJNy9lE/TRsKxLy2fZ47JAiQl+pYx4JBwgGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763301047; c=relaxed/simple; bh=LHmOSagoGoDV0/uRXaRtemJiXlLzQLZNDD+Rtm+uznQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=pV/buzbvhwZ/BYHf4tkEXdiQKZFZ/9hin28HMa0efUhwb57Mww16z4H+aRPNlBgjHeFzdbtJFwCEefV2vBajSjpB2rM5QZvtT+v6TIdhyopvFheBdeWzihtC8oLGXgTNssSdXEHLV8i5qc25d4n3IN9C9Gpu/E98Y7WkLUGkefg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl; spf=pass smtp.mailfrom=szczodrzynski.pl; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b=qbBlijiX; arc=none smtp.client-ip=46.242.128.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=szczodrzynski.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=szczodrzynski.pl header.i=@szczodrzynski.pl header.b="qbBlijiX" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=szczodrzynski.pl; s=x; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=a0Kp4ncgXY6sTHdsDfmoXcWbE0QEKFtuM3FlNwmz7Co=; b=qbBlijiXNWZOheJ7PwgvqkiDCw 7snZxi04vTfyb2uXMKsVmUgImMnwERrGXsmjV3QjJfIQ8FTfo10PP2Dt/VzePD8CTCkHXZMyDTGSJ HhSuqfvBu3txtITmW1XuEk8sRwzZBiB2ay8nnMoIuM2i1u9kJcboSQfvo4lGsTYGgUKuLzBZ+3Ych cdmq7N8LkS26azsHRhJTlaUwrkyNmJPe7O1daZkmi+xwmf8VGvnJOz3F3VVcaWdTRHNEjRlKVwBUa 7ITlj6K9Wrqyts+KP6wm4g4u721RHos1iSw4k+wzEXpii19yugg8LAnbnDsVfiUrBQdkh86b8uDlp qceDUKtQ==; Received: from [62.171.184.96] (helo=buildhost.contaboserver.net) by s2.avantea.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1vKd9F-0000000FXXt-0z9v; Sun, 16 Nov 2025 14:50:33 +0100 From: =?UTF-8?q?Kuba=20Szczodrzy=C5=84ski?= To: Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, parthiban@linumiz.com, paulk@sys-base.io Subject: [PATCH v3 6/6] riscv: dts: allwinner: d1s-t113: Add LVDS0 pins Date: Sun, 16 Nov 2025 14:50:28 +0100 Message-Id: <20251116135028.447614-1-kuba@szczodrzynski.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251116134609.447043-1-kuba@szczodrzynski.pl> References: <20251116134609.447043-1-kuba@szczodrzynski.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authenticated-Id: kuba@szczodrzynski.pl Add LVDS pins to the PIO since it's now supported on D1s/T113. Signed-off-by: Kuba Szczodrzy=C5=84ski --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi index 78aa61607..c4ce809be 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -108,6 +108,15 @@ i2s1_dout0_pin: i2s1-dout0-pin { function =3D "i2s1_dout"; }; =20 + /omit-if-no-ref/ + lcd_lvds0_pins: lcd-lvds0-pins { + pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9"; + function =3D "lvds0"; + drive-strength =3D <30>; + bias-disable; + }; + /omit-if-no-ref/ lcd_rgb666_pins: lcd-rgb666-pins { pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", --=20 2.25.1